quartus_ii_8.0中VHDL编写的 数字时钟

上传者: fanwenbinfan | 上传时间: 2024-01-03 12:08:30 | 文件大小: 427KB | 文件类型: RAR
VHDL 编写的既有:时分可调、整点报时功能的数字时钟。运行于quartus_ii_8.0软件

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</span>","children":null,"spread":false},{"title":"CLOCK.(2).cnf.cdb <span style='color:#111;'> 1.22KB </span>","children":null,"spread":false},{"title":"CLOCK.db_info <span style='color:#111;'> 136B </span>","children":null,"spread":false},{"title":"CLOCK.(5).cnf.hdb <span style='color:#111;'> 591B </span>","children":null,"spread":false},{"title":"CLOCK.(8).cnf.hdb <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"CLOCK.(4).cnf.cdb <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"CLOCK.(7).cnf.cdb <span style='color:#111;'> 1.98KB </span>","children":null,"spread":false},{"title":"CLOCK.(8).cnf.cdb <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"CLOCK.sgdiff.hdb <span style='color:#111;'> 12.19KB </span>","children":null,"spread":false},{"title":"CLOCK.(1).cnf.cdb <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"CLOCK.dbp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"CLOCK.asm.qmsg <span style='color:#111;'> 1.56KB </span>","children":null,"spread":false},{"title":"CLOCK.cmp.rdb <span style='color:#111;'> 26.54KB </span>","children":null,"spread":false},{"title":"CLOCK.(10).cnf.cdb <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"CLOCK.(7).cnf.hdb <span style='color:#111;'> 514B </span>","children":null,"spread":false},{"title":"CLOCK.fit.qmsg <span style='color:#111;'> 39.92KB </span>","children":null,"spread":false},{"title":"CLOCK.(1).cnf.hdb <span style='color:#111;'> 470B </span>","children":null,"spread":false},{"title":"CLOCK.rtlv_sg_swap.cdb <span style='color:#111;'> 1.62KB </span>","children":null,"spread":false},{"title":"CLOCK.sld_design_entry.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"CLOCK.(3).cnf.hdb <span style='color:#111;'> 512B </span>","children":null,"spread":false},{"title":"CLOCK.(6).cnf.cdb <span style='color:#111;'> 2.11KB </span>","children":null,"spread":false},{"title":"CLOCK.(0).cnf.cdb <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"CLOCK.signalprobe.cdb <span style='color:#111;'> 424B </span>","children":null,"spread":false},{"title":"CLOCK.(6).cnf.hdb <span style='color:#111;'> 592B </span>","children":null,"spread":false},{"title":"CLOCK.rtlv.hdb <span style='color:#111;'> 11.94KB </span>","children":null,"spread":false},{"title":"CLOCK.cmp.cdb <span style='color:#111;'> 38.80KB </span>","children":null,"spread":false},{"title":"CLOCK.cmp.qrpt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"CLOCK.pre_map.hdb <span style='color:#111;'> 11.97KB </span>","children":null,"spread":false},{"title":"CLOCK.tan.qmsg <span style='color:#111;'> 164.20KB </span>","children":null,"spread":false},{"title":"CLOCK.(10).cnf.hdb <span style='color:#111;'> 507B </span>","children":null,"spread":false},{"title":"CLOCK.asm_labs.ddb <span style='color:#111;'> 120.92KB </span>","children":null,"spread":false},{"title":"CLOCK.sgdiff.cdb <span style='color:#111;'> 9.40KB </span>","children":null,"spread":false},{"title":"CLOCK.hier_info <span style='color:#111;'> 11.27KB </span>","children":null,"spread":false},{"title":"CLOCK.sld_design_entry_dsc.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"CLOCK.eco.cdb <span style='color:#111;'> 141B </span>","children":null,"spread":false},{"title":"CLOCK.cmp.hdb <span style='color:#111;'> 11.54KB </span>","children":null,"spread":false},{"title":"CLOCK.(2).cnf.hdb <span style='color:#111;'> 445B </span>","children":null,"spread":false},{"title":"CLOCK.(9).cnf.hdb <span style='color:#111;'> 431B </span>","children":null,"spread":false},{"title":"CLOCK.(9).cnf.cdb <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"CLOCK.psp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"CLOCK.(0).cnf.hdb <span style='color:#111;'> 924B </span>","children":null,"spread":false},{"title":"CLOCK.map.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"CLOCK.(4).cnf.hdb <span style='color:#111;'> 483B </span>","children":null,"spread":false},{"title":"CLOCK.(5).cnf.cdb <span style='color:#111;'> 2.11KB </span>","children":null,"spread":false},{"title":"CLOCK.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"CLOCK.map.hdb <span style='color:#111;'> 11.14KB </span>","children":null,"spread":false},{"title":"CLOCK.hif <span style='color:#111;'> 4.80KB </span>","children":null,"spread":false},{"title":"CLOCK.rtlv_sg.cdb <span style='color:#111;'> 10.73KB </span>","children":null,"spread":false},{"title":"CLOCK.map.qmsg <span style='color:#111;'> 19.45KB </span>","children":null,"spread":false},{"title":"CLOCK.cmp.tdb <span style='color:#111;'> 32.92KB </span>","children":null,"spread":false},{"title":"CLOCK.cbx.xml <span style='color:#111;'> 87B </span>","children":null,"spread":false},{"title":"CLOCK.cmp0.ddb <span style='color:#111;'> 95.61KB </span>","children":null,"spread":false},{"title":"CLOCK.map.cdb <span style='color:#111;'> 10.04KB </span>","children":null,"spread":false},{"title":"CLOCK.cmp.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"CLOCK.pre_map.cdb <span style='color:#111;'> 9.53KB </span>","children":null,"spread":false}],"spread":false},{"title":"CLOCK.qpf <span style='color:#111;'> 905B </span>","children":null,"spread":false},{"title":"SECOND.VHDL <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false},{"title":"FENPIN_4HZ.VHDL <span style='color:#111;'> 733B </span>","children":null,"spread":false},{"title":"CLOCK.asm.rpt <span style='color:#111;'> 8.21KB </span>","children":null,"spread":false},{"title":"CLOCK.map.summary <span style='color:#111;'> 386B </span>","children":null,"spread":false},{"title":"HOUR.VHDL <span style='color:#111;'> 854B </span>","children":null,"spread":false},{"title":"CLOCK.fit.summary <span style='color:#111;'> 488B </span>","children":null,"spread":false},{"title":"CLOCK.cdf <span style='color:#111;'> 282B </span>","children":null,"spread":false},{"title":"CLOCK.map.rpt <span style='color:#111;'> 24.21KB </span>","children":null,"spread":false},{"title":"MSECOND.VHDL <span style='color:#111;'> 757B </span>","children":null,"spread":false},{"title":"CLOCK.qsf <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"CLOCK.fit.rpt <span style='color:#111;'> 89.50KB </span>","children":null,"spread":false},{"title":"CLOCK.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"CALL.VHDL <span style='color:#111;'> 823B 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