FPGA-Sparta3E-USART-Verilog程序

[{"title":"（ 11 个子文件 10KB ） FPGA-Sparta3E-USART-Verilog程序","children":[{"title":"serial_interface.v <span style='color:#111;'> 3.99KB </span>","children":null,"spread":false},{"title":"xmit_rcv_control.v <span style='color:#111;'> 12.00KB </span>","children":null,"spread":false},{"title":"uart_top.v <span style='color:#111;'> 2.95KB </span>","children":null,"spread":false},{"title":"tester.v <span style='color:#111;'> 6.28KB </span>","children":null,"spread":false},{"title":"control_operation.v <span style='color:#111;'> 3.19KB </span>","children":null,"spread":false},{"title":"clock_divider.v <span style='color:#111;'> 2.07KB </span>","children":null,"spread":false},{"title":"status_registers.v <span style='color:#111;'> 1.85KB </span>","children":null,"spread":false},{"title":"cpu_interface.v <span style='color:#111;'> 1.61KB </span>","children":null,"spread":false},{"title":"uart_tb.v <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"address_decode.v <span style='color:#111;'> 1.46KB </span>","children":null,"spread":false},{"title":"www.pudn.com.txt <span style='color:#111;'> 218B </span>","children":null,"spread":false}],"spread":true}]