四位无符号数乘法器的VHDL语言设计

上传者: ecologysysu | 上传时间: 2021-07-07 20:06:42 | 文件大小: 395KB | 文件类型: RAR
四位无符号数乘法器的VHDL语言设计,四位乘法器输入信号为a_in , b_in , 均为四位无符号数,输出为c_out, 为八位无符号数,有c_out = a_in × b_in 。程序设计中利用a_in与b_in (n) (n= 0, 1, 2, 3) 分别相乘后左移 n位再累加的方法来实现乘法功能。包含程序代码(VHD)、仿真波形图以及简单的设计报告。希望能给你提供一点帮助。

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评论信息

  • little_high :
    还不错,试验成功
    2015-05-06
  • qq_16589355 :
    通过设计的VHDL语言,实验顺利通过。
    2014-06-17
  • getdoc :
    没仿真出结果
    2013-11-18

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