流片验证过的wishbone接口的I2C总线verilog 代码

[{"title":"（ 22 个子文件 345KB ） 流片验证过的wishbone接口的I2C总线verilog 代码","children":[{"title":"trunk","children":[{"title":"software","children":[{"title":"include","children":[{"title":"oc_i2c_master.h <span style='color:#111;'> 5.59KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"rtl","children":[{"title":"vhdl","children":[{"title":"i2c_master_top.vhd <span style='color:#111;'> 13.14KB </span>","children":null,"spread":false},{"title":"i2c_master_byte_ctrl.vhd <span style='color:#111;'> 12.33KB </span>","children":null,"spread":false},{"title":"tst_ds1621.vhd <span style='color:#111;'> 6.80KB </span>","children":null,"spread":false},{"title":"i2c_master_bit_ctrl.vhd <span style='color:#111;'> 18.81KB </span>","children":null,"spread":false},{"title":"readme <span style='color:#111;'> 789B </span>","children":null,"spread":false},{"title":"I2C.VHD <span style='color:#111;'> 13.22KB </span>","children":null,"spread":false}],"spread":true},{"title":"verilog","children":[{"title":"i2c_master_top.v <span style='color:#111;'> 9.88KB </span>","children":null,"spread":false},{"title":"i2c_master_bit_ctrl.v <span style='color:#111;'> 17.91KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 23B </span>","children":null,"spread":false},{"title":"i2c_master_byte_ctrl.v <span style='color:#111;'> 10.30KB </span>","children":null,"spread":false},{"title":"i2c_master_defines.v <span style='color:#111;'> 2.94KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"sim","children":[{"title":"i2c_verilog","children":[{"title":"run","children":[{"title":"ncverilog.key <span style='color:#111;'> 5B </span>","children":null,"spread":false},{"title":"run <span style='color:#111;'> 514B </span>","children":null,"spread":false},{"title":"ncverilog.log <span style='color:#111;'> 4.59KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"doc","children":[{"title":"i2c_specs.pdf <span style='color:#111;'> 206.51KB </span>","children":null,"spread":false},{"title":"src","children":[{"title":"I2C_specs.doc <span style='color:#111;'> 454.00KB </span>","children":null,"spread":false},{"title":"~$C_specs.doc <span style='color:#111;'> 162B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"bench","children":[{"title":"verilog","children":[{"title":"i2c_slave_model.v <span style='color:#111;'> 11.16KB </span>","children":null,"spread":false},{"title":"spi_slave_model.v <span style='color:#111;'> 3.75KB </span>","children":null,"spread":false},{"title":"wb_master_model.v <span style='color:#111;'> 5.44KB </span>","children":null,"spread":false},{"title":"tst_bench_top.v <span style='color:#111;'> 14.15KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]