[{"title":"( 105 个子文件 503KB ) 精通VerilogHDL:IC设计核心技术实例详解(源代码)","children":[{"title":"EX3_4.bmp <span style='color:#111;'> 764.21KB </span>","children":null,"spread":false},{"title":"ex2_3.v <span style='color:#111;'> 487B </span>","children":null,"spread":false},{"title":"ex2_3.v.bak <span style='color:#111;'> 488B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 70B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 7.35KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]