4位加法器的VHDL（全套仿真实现）

[{"title":"（ 232 个子文件 375KB ） 4位加法器的VHDL（全套仿真实现）","children":[{"title":"adder.sim.rpt <span style='color:#111;'> 33.59KB </span>","children":null,"spread":false},{"title":"adder.fit.summary <span style='color:#111;'> 347B </span>","children":null,"spread":false},{"title":"adder.pin <span style='color:#111;'> 11.64KB </span>","children":null,"spread":false},{"title":"adder.db_info <span style='color:#111;'> 136B </span>","children":null,"spread":false},{"title":"adder.sim.rdb <span style='color:#111;'> 3.56KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]