VHDL 数字频率计设计
实验课需要用到 且调试通过~
LIBRARY IEEE ; --有时钟使能的十进制计数器
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY CNT10 IS
PORT (CLK : IN STD_LOGIC ; -- 计数时钟信号
CLR : IN STD_LOGIC ; -- 清零信号
ENA : IN STD_LOGIC ; -- 计数使能信号
CQ : OUT INTEGER RANGE 0 TO 15 ; -- 4 位计数结果输出
CARRY_OUT : OUT STD_LOGIC ) ; -- 计数进位
END CNT10 ;
。。。。。
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资源详情
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style='color:#111;'> 10.93KB </span>","children":null,"spread":false},{"title":"reg32b.fit <span style='color:#111;'> 8.06KB </span>","children":null,"spread":false},{"title":"U6764505.DLS <span style='color:#111;'> 1.12KB </span>","children":null,"spread":false},{"title":"U7001212.DLS <span style='color:#111;'> 6.25KB </span>","children":null,"spread":false},{"title":"testctl.fit <span style='color:#111;'> 2.01KB </span>","children":null,"spread":false},{"title":"testctl.vhd <span style='color:#111;'> 705B </span>","children":null,"spread":false},{"title":"reg32b.rpt <span style='color:#111;'> 27.74KB </span>","children":null,"spread":false},{"title":"reg32b.vhd <span style='color:#111;'> 373B </span>","children":null,"spread":false},{"title":"testctl.acf <span style='color:#111;'> 15.28KB </span>","children":null,"spread":false},{"title":"reg32b.ndb <span style='color:#111;'> 7.06KB </span>","children":null,"spread":false},{"title":"cnt10(5).cnf <span style='color:#111;'> 1.81KB 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