ISCA2018.rar

上传者: darknessdarkness | 上传时间: 2022-12-21 15:24:44 | 文件大小: 61.32MB | 文件类型: RAR
ISCA是计算机体系结构领域最权威的会议之一,会议论文被公认为芯片行业发展的风向标,该资源内含ISCA2018年的论文合集

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Platforms","children":[{"title":"Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer.pdf <span style='color:#111;'> 1.54MB </span>","children":null,"spread":false},{"title":"Euphrates_Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision.pdf <span style='color:#111;'> 7.69MB </span>","children":null,"spread":false},{"title":"Stitch_Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables.pdf <span style='color:#111;'> 2.30MB </span>","children":null,"spread":false},{"title":"EVA²_Exploiting Temporal Redundancy in Live Computer Vision.pdf <span style='color:#111;'> 983.77KB </span>","children":null,"spread":false},{"title":"Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems.pdf <span style='color:#111;'> 1020.09KB </span>","children":null,"spread":false}],"spread":true},{"title":"Machine Learning Systems 1","children":[{"title":"UCNN_Exploiting Computational Reuse in Deep Neural Networks via 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Algorithm to Accommodate Prefetching.pdf <span style='color:#111;'> 2.58MB </span>","children":null,"spread":false}],"spread":true},{"title":"Clouds&Datacenters","children":[{"title":"FireSim_FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.pdf <span style='color:#111;'> 1.04MB </span>","children":null,"spread":false},{"title":"A Configurable Cloud-Scale DNN Processor for Real_Time AI.pdf <span style='color:#111;'> 271.78KB </span>","children":null,"spread":false},{"title":"Virtual Melting Temperature_Managing Server Load to Minimize Cooling Overhead with Phase Change Materials.pdf <span style='color:#111;'> 1.14MB </span>","children":null,"spread":false}],"spread":true},{"title":"Security","children":[{"title":"Mobilizing the Micro-Ops_Exploiting Context Sensitive Decoding for Security and Energy Efficiency.pdf <span style='color:#111;'> 2.62MB </span>","children":null,"spread":false},{"title":"Hiding Intermittent Information Leakage with Architectural Support for Blinking.pdf <span style='color:#111;'> 389.60KB </span>","children":null,"spread":false},{"title":"Mitigating Wordline Crosstalk using Adaptive Trees of Counters.pdf <span style='color:#111;'> 1.39MB </span>","children":null,"spread":false},{"title":"Nonblocking Memory Refresh.pdf <span style='color:#111;'> 894.90KB </span>","children":null,"spread":false},{"title":"Practical Memory Safety with REST.pdf <span style='color:#111;'> 399.29KB </span>","children":null,"spread":false}],"spread":true},{"title":"Virtual Memory","children":[{"title":"SEESAW_Using Superpages to Improve VIPT Caches.pdf <span style='color:#111;'> 903.99KB </span>","children":null,"spread":false},{"title":"Scheduling Page Table Walks for Irregular GPU Applications.pdf <span style='color:#111;'> 1.44MB </span>","children":null,"spread":false},{"title":"Get Out of the Valley_Power-Efficient Address Mapping for GPUs.pdf <span style='color:#111;'> 357.42KB </span>","children":null,"spread":false},{"title":"A Case for Richer Cross-Layer Abstractions_Bridging the Semantic Gap with Expressive Memory.pdf <span style='color:#111;'> 335.45KB </span>","children":null,"spread":false}],"spread":true},{"title":"Emerging Memory 2","children":[{"title":"Lazy Persistency_A High-Performing and Write-Efficient Software Persistency Technique.pdf <span style='color:#111;'> 1.21MB </span>","children":null,"spread":false},{"title":"Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability.pdf <span style='color:#111;'> 646.20KB </span>","children":null,"spread":false},{"title":"DHTM_Durable Hardware Transactional Memory.pdf <span style='color:#111;'> 370.68KB </span>","children":null,"spread":false}],"spread":true},{"title":"Interconnection Networks","children":[{"title":"TCEP_Traffic Consolidation for Energy-Proportional High-Radix Networks.pdf <span style='color:#111;'> 467.83KB </span>","children":null,"spread":false},{"title":"FastTrack_Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs.pdf <span style='color:#111;'> 254.71KB </span>","children":null,"spread":false},{"title":"Modular Routing Design for Chiplet-based Systems.pdf <span style='color:#111;'> 1.07MB </span>","children":null,"spread":false},{"title":"Synchronized Progress in Interconnection Networks (SPIN)_A New Theory for Deadlock Freedom.pdf <span style='color:#111;'> 9.15MB </span>","children":null,"spread":false}],"spread":true},{"title":"Emerging Memory 1","children":[{"title":"Neural Cache_Bit-Serial In-Cache Acceleration of Deep Neural Networks.pdf <span style='color:#111;'> 3.89MB </span>","children":null,"spread":false},{"title":"Scaling Datacenter Accelerators with Compute-Reuse Architectures.pdf <span style='color:#111;'> 2.22MB </span>","children":null,"spread":false},{"title":"Enabling Scientific Computing on Memristive Accelerators.pdf <span style='color:#111;'> 851.29KB </span>","children":null,"spread":false}],"spread":false},{"title":"Emerging Paradigms","children":[{"title":"Flexon_A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations.pdf <span style='color:#111;'> 440.96KB </span>","children":null,"spread":false},{"title":"Architecting a Stochastic Computing Unit with Molecular Optical Devices.pdf <span style='color:#111;'> 1.44MB </span>","children":null,"spread":false},{"title":"Space-Time Algebra_A Model for Neocortical Computation.pdf <span style='color:#111;'> 275.96KB </span>","children":null,"spread":false}],"spread":false},{"title":"GPUs","children":[{"title":"The Locality Descriptor_A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs.pdf <span style='color:#111;'> 604.35KB </span>","children":null,"spread":false},{"title":"Generic System Calls for GPUs.pdf <span style='color:#111;'> 863.78KB </span>","children":null,"spread":false},{"title":"RegMutex_Inter-Warp GPU Register Time-Sharing.pdf <span style='color:#111;'> 767.61KB </span>","children":null,"spread":false},{"title":"HetCore_TFET-CMOS Hetero-Device Architecture for CPUs and GPUs.pdf <span style='color:#111;'> 1.32MB </span>","children":null,"spread":false}],"spread":false},{"title":"Controllers & Control Systems","children":[{"title":"Yukta_Multilayer Resource Controllers to Maximize Efficiency.pdf <span style='color:#111;'> 789.24KB </span>","children":null,"spread":false},{"title":"RoboX_An End-to-End Solution to Accelerate Autonomous Control in Robotics.pdf <span style='color:#111;'> 767.25KB </span>","children":null,"spread":false},{"title":"DCS-ctrl_A Fast and Flexible Device-Control Mechanism for Device-Centric Server Architecture.pdf <span style='color:#111;'> 446.03KB </span>","children":null,"spread":false}],"spread":false},{"title":"Machine Learning Systems 2","children":[{"title":"Bit Fusion-Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.pdf 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