UART控制器的vhdl和verilog源码

[{"title":"（ 10 个子文件 145KB ） UART控制器的vhdl和verilog源码","children":[{"title":"uart","children":[{"title":"RXCVER.VHD <span style='color:#111;'> 6.27KB </span>","children":null,"spread":false},{"title":"UART.V <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false},{"title":"UART.TB <span style='color:#111;'> 4.78KB </span>","children":null,"spread":false},{"title":"RXCVER.V <span style='color:#111;'> 6.29KB </span>","children":null,"spread":false},{"title":"UART.TF <span style='color:#111;'> 3.56KB </span>","children":null,"spread":false},{"title":"VERSION.TXT <span style='color:#111;'> 682B </span>","children":null,"spread":false},{"title":"TXMIT.V <span style='color:#111;'> 5.09KB </span>","children":null,"spread":false},{"title":"QAN20.PDF <span style='color:#111;'> 205.67KB </span>","children":null,"spread":false},{"title":"UART.VHD <span style='color:#111;'> 1.78KB </span>","children":null,"spread":false},{"title":"TXMIT.VHD <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]