[{"title":"( 68 个子文件 375KB ) 利用verilog来实现四位数码管0到9的循环计数","children":[{"title":"SegStaticDisp(3)","children":[{"title":"display.v <span style='color:#111;'> 2.74KB </span>","children":null,"spread":false},{"title":"SegStaticDisp.fit.rpt <span style='color:#111;'> 60.17KB </span>","children":null,"spread":false},{"title":"SegStaticDisp.fit.smsg <span style='color:#111;'> 334B </span>","children":null,"spread":false},{"title":"SegStaticDisp.map.smsg <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"SegStaticDisp.pin <span style='color:#111;'> 14.45KB </span>","children":null,"spread":false},{"title":"SegStaticDisp.qws <span style='color:#111;'> 537B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"SegStaticDisp.eco.cdb <span style='color:#111;'> 161B </span>","children":null,"spread":false},{"title":"SegStaticDisp.pre_map.cdb <span style='color:#111;'> 18.83KB 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