[{"title":"( 12 个子文件 316KB ) FPGA-Audio-IIR-master.zip","children":[{"title":"FPGA-Audio-IIR-master","children":[{"title":"audiosystem.vhd <span style='color:#111;'> 4.37KB </span>","children":null,"spread":false},{"title":"main_bitmap.bin <span style='color:#111;'> 132.01KB </span>","children":null,"spread":false},{"title":"top.vhd <span style='color:#111;'> 2.00KB </span>","children":null,"spread":false},{"title":"sim_i2s_rxtx.png <span style='color:#111;'> 31.10KB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 910B </span>","children":null,"spread":false},{"title":"pins.pcf <span style='color:#111;'> 627B </span>","children":null,"spread":false},{"title":"i2s_rxtx.vhd <span style='color:#111;'> 2.36KB </span>","children":null,"spread":false},{"title":"iir.vhd <span style='color:#111;'> 3.55KB </span>","children":null,"spread":false},{"title":"sim_iir.png <span style='color:#111;'> 16.39KB </span>","children":null,"spread":false},{"title":"documentation.pdf <span style='color:#111;'> 235.41KB </span>","children":null,"spread":false},{"title":"pll.vhd <span style='color:#111;'> 3.89KB </span>","children":null,"spread":false},{"title":"clk.sdc <span style='color:#111;'> 372B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]