用VHDL语言仿真闹钟设计

[{"title":"（ 129 个子文件 289KB ） 用VHDL语言仿真闹钟设计","children":[{"title":"使用说明请参看右侧注释====〉〉.txt <span style='color:#111;'> 774B </span>","children":null,"spread":false},{"title":"fq_divider.tan.rpt <span style='color:#111;'> 28.41KB </span>","children":null,"spread":false},{"title":"time_lock.tan.summary <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"time_lock.fit.eqn <span style='color:#111;'> 10.13KB </span>","children":null,"spread":false},{"title":"fq_divider.bmp <span style='color:#111;'> 172.71KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]