数字钟verilog语言实现

上传者: chichimeimei | 上传时间: 2024-01-04 18:46:00 | 文件大小: 642KB | 文件类型: RAR
这是用verilog语言实现的数字钟,以FPGA为应用平台,实现了精确计时,以及电台报时和闹钟等功能

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