FPGA浮点数加减乘除基于verilogHDL

[{"title":"（ 8 个子文件 17KB ） FPGA浮点数加减乘除基于verilogHDL","children":[{"title":"fpu","children":[{"title":"e1.qpf <span style='color:#111;'> 1.31KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"e1.db_info <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"e1.sld_design_entry.sci <span style='color:#111;'> 270B </span>","children":null,"spread":false}],"spread":true},{"title":"fpu.v <span style='color:#111;'> 139.69KB </span>","children":null,"spread":false},{"title":"fpu.qip <span style='color:#111;'> 346B </span>","children":null,"spread":false},{"title":"e1.qws <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"e1.qsf <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"fpu_bb.v <span style='color:#111;'> 3.59KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]