用vhdl实现8259设计

[{"title":"（ 30 个子文件 26KB ） 用vhdl实现8259设计","children":[{"title":"8259VHDL程序","children":[{"title":"rw_cntl.vhd <span style='color:#111;'> 8.98KB </span>","children":null,"spread":false},{"title":"a8259.vhd <span style='color:#111;'> 8.58KB </span>","children":null,"spread":false},{"title":"vect_mux.vhd <span style='color:#111;'> 740B </span>","children":null,"spread":false},{"title":"ocw_dcde.scf <span style='color:#111;'> 733B </span>","children":null,"spread":false},{"title":"initcntl.scf <span style='color:#111;'> 1.33KB </span>","children":null,"spread":false},{"title":"initcntl.vhd <span style='color:#111;'> 5.20KB </span>","children":null,"spread":false},{"title":"ocw3_reg.vhd <span style='color:#111;'> 2.23KB </span>","children":null,"spread":false},{"title":"cwrd_reg.vhd <span style='color:#111;'> 1.32KB </span>","children":null,"spread":false},{"title":"ocw3_reg.scf <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false},{"title":"pri_res.scf <span style='color:#111;'> 1.81KB </span>","children":null,"spread":false},{"title":"is_reg.scf <span style='color:#111;'> 2.44KB </span>","children":null,"spread":false},{"title":"rw_cntl_init.scf <span style='color:#111;'> 4.52KB </span>","children":null,"spread":false},{"title":"int_ltch.scf <span style='color:#111;'> 3.67KB </span>","children":null,"spread":false},{"title":"int_ltch.vhd <span style='color:#111;'> 2.52KB </span>","children":null,"spread":false},{"title":"ocw_dcde.vhd <span style='color:#111;'> 1.33KB </span>","children":null,"spread":false},{"title":"is_reg.vhd <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"seq_cntl.scf <span style='color:#111;'> 3.05KB </span>","children":null,"spread":false},{"title":"a8259.scf <span style='color:#111;'> 24.69KB </span>","children":null,"spread":false},{"title":"rw_cntl.scf <span style='color:#111;'> 6.52KB </span>","children":null,"spread":false},{"title":"rd_mux.vhd <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"int_seq.scf <span style='color:#111;'> 4.60KB </span>","children":null,"spread":false},{"title":"ir_reg.vhd <span style='color:#111;'> 1.55KB </span>","children":null,"spread":false},{"title":"vect_mux.scf <span style='color:#111;'> 3.24KB </span>","children":null,"spread":false},{"title":"ocw2_reg.vhd <span style='color:#111;'> 4.67KB </span>","children":null,"spread":false},{"title":"int_seq.vhd <span style='color:#111;'> 5.07KB </span>","children":null,"spread":false},{"title":"seq_cntl.vhd <span style='color:#111;'> 10.96KB </span>","children":null,"spread":false},{"title":"ir_reg.scf <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"ocw2_reg.scf <span style='color:#111;'> 1.94KB </span>","children":null,"spread":false},{"title":"pri_res.vhd <span style='color:#111;'> 3.78KB </span>","children":null,"spread":false},{"title":"rd_mux.scf <span style='color:#111;'> 3.14KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]