FPGA 60计时

上传者: byjjing | 上传时间: 2019-12-21 19:30:15 | 文件大小: 139KB | 文件类型: rar
60进制计数 可以做秒和分钟的计时 entity jishu60 is port(s:in std_logic;--置位信号(低电平有效) clk:in std_logic;--时钟信号 data:in std_logic_vector(5 downto 0);--预置数 num:buffer std_logic_vector(5 downto 0);--计数结果 co: out std_logic);--进位信号

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