FPGA A7 + USB3.0 收发同步进行，带控制收发通道。代码精简，Vivado2019

[{"title":"（ 1714 个子文件 547.82MB ） FPGA A7 + USB3.0 收发同步进行，带控制收发通道。代码精简，Vivado2019","children":[{"title":"SlaveFifoSync.img <span style='color:#111;'> 99.28KB </span>","children":null,"spread":false},{"title":"top.bit <span style='color:#111;'> 3.65MB </span>","children":null,"spread":false},{"title":"ddr3_pinout.ucf <span style='color:#111;'> 4.92KB </span>","children":null,"spread":false},{"title":"AN70983_Designing_a_Bulk_Transfer_Host_Application_for_EZ_USB_R_FX2LP_TM_FX3_TM_Chinese.pdf <span style='color:#111;'> 975.81KB </span>","children":null,"spread":false},{"title":"AN84868_Configuring_an_FPGA_over_USB_Using_Cypress_EZ-USB_FX3_Chinese.pdf <span style='color:#111;'> 1.57MB </span>","children":null,"spread":false},{"title":"AN75705_Getting_Started_With_EZ-USB_R_FX3_TM_Chinese.pdf <span style='color:#111;'> 2.04MB </span>","children":null,"spread":false},{"title":"AN84868 - Source files for FX3 Firmware.zip <span style='color:#111;'> 3.70MB </span>","children":null,"spread":false},{"title":"FX3SDKSetup_1.3.4.exe <span style='color:#111;'> 374.92MB </span>","children":null,"spread":false},{"title":"AN65974_Designing_with_the_EZ-USB_FX3_Slave_FIFO_Interface_Chinese.pdf <span style='color:#111;'> 3.24MB </span>","children":null,"spread":false},{"title":"AN70983.zip <span style='color:#111;'> 10.06MB </span>","children":null,"spread":false},{"title":"AN65974_Slave_fifo.zip <span style='color:#111;'> 10.09MB </span>","children":null,"spread":false},{"title":"USB3_GPIF测试.pdf <span style='color:#111;'> 297.08KB </span>","children":null,"spread":false},{"title":".project <span style='color:#111;'> 791B </span>","children":null,"spread":false},{"title":"cyfxslfifosync.h <span style='color:#111;'> 4.18KB </span>","children":null,"spread":false},{"title":".cproject <span style='color:#111;'> 73.55KB </span>","children":null,"spread":false},{"title":"language.settings.xml <span style='color:#111;'> 4.28KB </span>","children":null,"spread":false},{"title":"cyfxslfifosync.c <span style='color:#111;'> 36.02KB </span>","children":null,"spread":false},{"title":"cyfx_gcc_startup.S <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"makefile <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"cyfxtx.c <span style='color:#111;'> 39.44KB </span>","children":null,"spread":false},{"title":"cyfxgpif2config.h <span style='color:#111;'> 7.05KB </span>","children":null,"spread":false},{"title":"cyfxslfifousbdscr.c <span style='color:#111;'> 19.19KB </span>","children":null,"spread":false},{"title":"readme.txt <span style='color:#111;'> 2.67KB </span>","children":null,"spread":false},{"title":"DS_FT2232H.pdf <span style='color:#111;'> 1.97MB </span>","children":null,"spread":false},{"title":"ug475_7Series_Pkg_Pinout.pdf <span style='color:#111;'> 29.47MB </span>","children":null,"spread":false},{"title":"4Gb_DDR3_SDRAM_MT41J.pdf <span style='color:#111;'> 11.26MB </span>","children":null,"spread":false},{"title":"CYUSB301X_CYUSB201X_001-52136_0Q_V.pdf <span style='color:#111;'> 1.11MB </span>","children":null,"spread":false},{"title":"AN86947.zip <span style='color:#111;'> 14.50MB </span>","children":null,"spread":false},{"title":"ug908-vivado-programming-debugging.pdf <span style='color:#111;'> 8.49MB </span>","children":null,"spread":false},{"title":"ug470_7Series_Config.pdf <span style='color:#111;'> 5.72MB </span>","children":null,"spread":false},{"title":"top.xdc <span style='color:#111;'> 5.06KB </span>","children":null,"spread":false},{"title":"fifo_generator_vlog_beh.v <span style='color:#111;'> 441.59KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_vhsyn_rfs.vhd <span style='color:#111;'> 2.34MB </span>","children":null,"spread":false},{"title":"blk_mem_gen_v8_4_vhsyn_rfs.vhd <span style='color:#111;'> 14.18MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.v <span style='color:#111;'> 582.13KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.vhd <span style='color:#111;'> 1.38MB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.xci <span style='color:#111;'> 73.73KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.vhd <span style='color:#111;'> 39.57KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.veo <span style='color:#111;'> 3.69KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_stub.vhdl <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.vho <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.xdc <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_sim_netlist.v <span style='color:#111;'> 347.46KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_stub.v <span style='color:#111;'> 1.87KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_sim_netlist.vhdl <span style='color:#111;'> 424.24KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.dcp <span style='color:#111;'> 190.31KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.xml <span style='color:#111;'> 596.07KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_changelog.txt <span style='color:#111;'> 11.08KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo.v <span style='color:#111;'> 15.79KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_ooc.xdc <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo_stub.vhdl <span style='color:#111;'> 1.81KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.veo <span style='color:#111;'> 3.52KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo_ooc.xdc <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"fifo_generator_vlog_beh.v <span style='color:#111;'> 441.59KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo_stub.v <span style='color:#111;'> 1.78KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.xdc <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_vhsyn_rfs.vhd <span style='color:#111;'> 2.34MB </span>","children":null,"spread":false},{"title":"blk_mem_gen_v8_4_vhsyn_rfs.vhd <span style='color:#111;'> 14.18MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.v <span style='color:#111;'> 582.13KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.vhd <span style='color:#111;'> 1.38MB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.dcp <span style='color:#111;'> 189.94KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.xci <span style='color:#111;'> 73.59KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.vhd <span style='color:#111;'> 39.47KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.vho <span style='color:#111;'> 3.80KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo_sim_netlist.vhdl <span style='color:#111;'> 432.31KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.xml <span style='color:#111;'> 596.00KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_changelog.txt <span style='color:#111;'> 11.08KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo.v <span style='color:#111;'> 15.68KB </span>","children":null,"spread":false},{"title":"hs_rx_pkt_fifo_sim_netlist.v <span style='color:#111;'> 355.26KB </span>","children":null,"spread":false},{"title":"data_fifo_stub.v <span style='color:#111;'> 1.87KB </span>","children":null,"spread":false},{"title":"fifo_generator_vlog_beh.v <span style='color:#111;'> 441.59KB </span>","children":null,"spread":false},{"title":"data_fifo.xdc <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"data_fifo_sim_netlist.vhdl <span style='color:#111;'> 208.45KB </span>","children":null,"spread":false},{"title":"data_fifo_ooc.xdc <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_vhsyn_rfs.vhd <span style='color:#111;'> 2.34MB </span>","children":null,"spread":false},{"title":"blk_mem_gen_v8_4_vhsyn_rfs.vhd <span style='color:#111;'> 14.18MB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.v <span style='color:#111;'> 582.13KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_rfs.vhd <span style='color:#111;'> 1.38MB </span>","children":null,"spread":false},{"title":"data_fifo.vho <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"data_fifo.vhd <span style='color:#111;'> 39.55KB </span>","children":null,"spread":false},{"title":"data_fifo.xci <span style='color:#111;'> 73.72KB </span>","children":null,"spread":false},{"title":"data_fifo_stub.vhdl <span style='color:#111;'> 1.88KB </span>","children":null,"spread":false},{"title":"data_fifo.dcp <span style='color:#111;'> 114.54KB </span>","children":null,"spread":false},{"title":"data_fifo_sim_netlist.v <span style='color:#111;'> 155.34KB </span>","children":null,"spread":false},{"title":"data_fifo.xml <span style='color:#111;'> 596.05KB </span>","children":null,"spread":false},{"title":"fifo_generator_v13_2_changelog.txt <span style='color:#111;'> 11.08KB </span>","children":null,"spread":false},{"title":"data_fifo.veo <span style='color:#111;'> 3.69KB </span>","children":null,"spread":false},{"title":"data_fifo.v <span style='color:#111;'> 15.79KB </span>","children":null,"spread":false},{"title":"top.v <span style='color:#111;'> 6.21KB </span>","children":null,"spread":false},{"title":"gpif2_to_fifo32.v <span style='color:#111;'> 21.26KB </span>","children":null,"spread":false},{"title":"project.wdf <span style='color:#111;'> 3.88KB </span>","children":null,"spread":false},{"title":"rundef.js <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"runme.sh <span style='color:#111;'> 1.20KB </span>","children":null,"spread":false},{"title":"dont_touch.xdc <span style='color:#111;'> 1.75KB </span>","children":null,"spread":false},{"title":"vivado.jou <span style='color:#111;'> 806B </span>","children":null,"spread":false},{"title":"hs_tx_fifo.vds <span style='color:#111;'> 99.89KB </span>","children":null,"spread":false},{"title":".vivado.end.rst <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"ISEWrap.sh <span style='color:#111;'> 1.76KB </span>","children":null,"spread":false},{"title":"hs_tx_fifo_utilization_synth.rpt <span style='color:#111;'> 7.32KB </span>","children":null,"spread":false},{"title":"vivado.pb <span style='color:#111;'> 145.42KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]