Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料

Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module spi_flash_top( input sys_clk, input rst, output nCS, output DCLK, output MOSI, input MISO, input[15:0] clk_div, input[3:0] cmd, input cmd_valid, output cmd_ack, input[23:0] addr, input[7:0] data_in, input[8:0] size, output data_req, output reg[7:0] data_out, output reg data_valid ); localparam S_IDLE = 0; localparam S_SE = 1; localparam S_BE = 2; localparam S_READ = 3; localparam S_WRITE = 4; localparam S_ACK = 5; localparam S_CK_STATE = 6; //present state monitor localparam S_WREN = 7; wire spi_flash_cmd_ack; reg[3:0] sub_cmd; reg sub_cmd_valid; reg[8:0] sub_size; reg[4:0] state,next_state; reg[7:0] state_reg; wire sub_data_valid; wire[7:0] sub_data_in; wire[7:0] sub_data_out; assign sub_data_in = data_in; assign cmd_ack = (state == S_ACK); always@(posedge sys_clk or posedge rst) begin if(rst==1) state <= S_IDLE; else state <= next_state; end always@(*) begin case(state) S_IDLE: if(cmd_valid && cmd == `CMD_BE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_SE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_READ) next_state <= S_READ; else if(cmd_valid && cmd == `CMD_PP) next_state <= S_WREN; else next_state <= S_IDLE; S_WREN: if(spi_flash_cmd_ack && cmd == `CMD_BE) next_state <= S_BE; else if(spi_flash_cmd_ack && cmd == `CMD_SE) next_state <= S_SE; else if(spi_flash_cmd_ack && cmd == `CMD_PP) next_state <= S_WRITE; else next_state <= S_WREN; S_BE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;//读取状态寄存器 else next_state <= S_BE; S_SE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;