上传者: SKCQTGZX
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上传时间: 2021-12-02 13:02:55
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文件大小: 2.23MB
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文件类型: ZIP
SDRAM硬件控制FPGA读写verilog设计实验Quartus9.1工程源码,可以做为你的学习设计基参考。
module SDRAM_HR_HW (
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [17:0] LEDR,
output [6:0] HEX0,
HEX1,
//SDRAM side
output [11:0] DRAM_ADDR,
inout [15:0] DRAM_DQ,
output DRAM_BA_0,
DRAM_BA_1,
DRAM_RAS_N,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_WE_N,
DRAM_CS_N,
DRAM_LDQM,
DRAM_UDQM
);
reg read; // read enable register
reg write; // write enable register
reg [1:0] state; // FSM state register
reg [15:0] data_in; // data input register
wire [15:0] DATA_OUT; // data output
reg [15:0] data_out; // data output register
wire DELAY_RESET; // delay for SDRAM controller load
wire RESET_n = KEY[0]; // reset from KEY[0]
assign LEDR = SW;
Sdram_Control_4Port u0 (
// HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA(data_in),
.WR1(write),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512*2),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DELAY_RESET),
.WR1_CLK(CLOCK_50),
// FIFO Read Side 1
.RD1_DATA(DATA_OUT),
.RD1(read),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DELAY_RESET),
.RD1_CLK(CLOCK_50),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK)
);
wire HEX3,HEX4,HEX5,HEX6,HEX7;
SEG7_LUT_8 u1 (
.oSEG0(HEX0), // output SEG0
.oSEG1(HEX1), // output SEG1
.oSEG2(HEX2), // output SEG2
.oSEG3(HEX3), // output SEG3
.oSEG4(HEX4), // output SEG4
.oSEG5(HEX5), // output SEG5
.oSEG6(HEX6), // output SEG6
.oSEG7(HEX7), // outp