基于FPGA的数字秒表设计

[{"title":"（ 132 个子文件 2.61MB ） 基于FPGA的数字秒表设计","children":[{"title":"time_clock.qsf <span style='color:#111;'> 5.06KB </span>","children":null,"spread":false},{"title":"time_clock.qpf <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"time_clock.sim.rpt <span style='color:#111;'> 322.53KB </span>","children":null,"spread":false},{"title":"time_clock.sim.rdb <span style='color:#111;'> 17.93KB </span>","children":null,"spread":false},{"title":"time_clock.lpc.rdb <span style='color:#111;'> 385B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]