VHDL实现DDS的数字移相信号发生器的设计代码

[{"title":"（ 41 个子文件 118KB ） VHDL实现DDS的数字移相信号发生器的设计代码","children":[{"title":"EXPT12_10_PHAS_PLL1","children":[{"title":"EXPT12_10_PHAS_PLL","children":[{"title":"ADDER10B.VHD <span style='color:#111;'> 349B </span>","children":null,"spread":false},{"title":"PLL20.VHD <span style='color:#111;'> 9.47KB </span>","children":null,"spread":false},{"title":"dds_vhdl.flow.rpt <span style='color:#111;'> 4.00KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.QSF <span style='color:#111;'> 5.29KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.QPF <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"cmp_state.ini <span style='color:#111;'> 3B </span>","children":null,"spread":false},{"title":"REG10B.VHD <span style='color:#111;'> 441B </span>","children":null,"spread":false},{"title":"DDS_VHDL.VHD <span style='color:#111;'> 2.75KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"cntr_kv8.tdf <span style='color:#111;'> 5.29KB </span>","children":null,"spread":false},{"title":"altsyncram_t5b2.tdf <span style='color:#111;'> 20.16KB </span>","children":null,"spread":false},{"title":"dds_vhdl.sld_design_entry.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"dds_vhdl.eco.cdb <span style='color:#111;'> 141B </span>","children":null,"spread":false},{"title":"cntr_pd8.tdf <span style='color:#111;'> 4.05KB </span>","children":null,"spread":false},{"title":"altsyncram_m9t.tdf <span style='color:#111;'> 3.29KB </span>","children":null,"spread":false},{"title":"dds_vhdl.db_info <span style='color:#111;'> 136B </span>","children":null,"spread":false},{"title":"decode_9ie.tdf <span style='color:#111;'> 4.12KB </span>","children":null,"spread":false},{"title":"dds_vhdl_cmp.qrpt <span style='color:#111;'> 0B </span>","children":null,"spread":false}],"spread":true},{"title":"PLL20.BSF <span style='color:#111;'> 3.70KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.PIN <span style='color:#111;'> 29.92KB </span>","children":null,"spread":false},{"title":"dds_vhdl.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"ADDER32B.VHD <span style='color:#111;'> 350B </span>","children":null,"spread":false},{"title":"dds_vhdl_assignment_defaults.qdf <span style='color:#111;'> 28.67KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.QWS <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false},{"title":"dds_vhdl.map.rpt <span style='color:#111;'> 49.23KB </span>","children":null,"spread":false},{"title":"REG32B.VHD <span style='color:#111;'> 441B </span>","children":null,"spread":false},{"title":"dds_vhdl.map.eqn <span style='color:#111;'> 147.95KB </span>","children":null,"spread":false},{"title":"dds_vhdl.fit.summary <span style='color:#111;'> 397B </span>","children":null,"spread":false},{"title":"README","children":[{"title":"readme.txt <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false}],"spread":false},{"title":"dds_vhdl.tan.summary <span style='color:#111;'> 3.08KB </span>","children":null,"spread":false},{"title":"dds_vhdl.asm.rpt <span style='color:#111;'> 8.41KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.CDF <span style='color:#111;'> 333B </span>","children":null,"spread":false},{"title":"dds_vhdl.map.summary <span style='color:#111;'> 334B </span>","children":null,"spread":false},{"title":"SIN_ROM.VHD <span style='color:#111;'> 6.40KB </span>","children":null,"spread":false},{"title":"dds_vhdl.fit.rpt <span style='color:#111;'> 129.05KB </span>","children":null,"spread":false},{"title":"dds_vhdl.pof <span style='color:#111;'> 128.14KB </span>","children":null,"spread":false},{"title":"DATA","children":[{"title":"LUT10X10.MIF <span style='color:#111;'> 14.83KB </span>","children":null,"spread":false},{"title":"LUT10X10.HEX <span style='color:#111;'> 17.01KB </span>","children":null,"spread":false}],"spread":false},{"title":"DDS_VHDL.SOF <span style='color:#111;'> 274.93KB </span>","children":null,"spread":false},{"title":"dds_vhdl.fit.eqn <span style='color:#111;'> 166.46KB </span>","children":null,"spread":false},{"title":"dds_vhdl.tan.rpt <span style='color:#111;'> 436.60KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"www.pudn.com.txt <span style='color:#111;'> 218B </span>","children":null,"spread":false}],"spread":true}]