Tiva单片机+Cyclone IV E实现全桥单相逆变电路，单片机和FPGA代码
本系统以TM4C123GH6PM 单片机/FPGA 为控制核心，基于正弦脉冲宽度
调制（SPWM），设计制作了单相正弦波逆变电源，实现了输入15V 直流电压，
输出有效值为10V、额定功率为10W 的正弦交流电压，交流频率在20Hz 至100Hz
内能以1Hz 为步进值进行调整。系统使用TM4C123GH6PM 单片机/FPGA 产生
SPWM 波控制全桥电路，桥路输出信号经LC 滤波电路后得到失真度小于0.5%
的正弦波；系统采用PID 控制算法使输出交流电压负载调整率低于1%；通过合
理选用MOSFET 等措施使系统效率达到89%；采用互感器和AD 采样芯片获得
输出电流与输出电压，通过FPGA 控制继电器实现输出过流保护和自恢复功能。
系统可通过键盘步进控制和蓝牙控制两种方式设置交流频率，通过LCD 屏幕和
蓝牙接收设备实时显示系统工作参数，人机交互良好。经测试，系统除输出效率
外达到题目的全部指标要求。
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[{"title":"（ 599 个子文件 13.96MB ） Tiva单片机+Cyclone IV E实现全桥单相逆变电路，单片机和FPGA代码","children":[{"title":"_info <span style='color:#111;'> 5.85KB </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.vpr.ammdb <span style='color:#111;'> 5.49KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.root_partition.cmp.ammdb <span style='color:#111;'> 3.60KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autos_3e921.cmp.ammdb <span style='color:#111;'> 2.19KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autoh_e40e1.cmp.ammdb <span style='color:#111;'> 596B </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.map.ammdb <span style='color:#111;'> 133B </span>","children":null,"spread":false},{"title":"ads8688.v.bak <span style='color:#111;'> 11.67KB </span>","children":null,"spread":false},{"title":"mult_16_16_s.v.bak <span style='color:#111;'> 4.42KB </span>","children":null,"spread":false},{"title":"mult_23_16_s.v.bak <span style='color:#111;'> 4.42KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.qsf.bak <span style='color:#111;'> 3.76KB </span>","children":null,"spread":false},{"title":"top_module.vt.bak <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak <span style='color:#111;'> 2.20KB </span>","children":null,"spread":false},{"title":"clkdiv.v.bak <span style='color:#111;'> 2.06KB </span>","children":null,"spread":false},{"title":"top_module.v.bak <span style='color:#111;'> 2.04KB </span>","children":null,"spread":false},{"title":"BUS.v.bak <span style='color:#111;'> 836B </span>","children":null,"spread":false},{"title":"pwm.v.bak <span style='color:#111;'> 718B </span>","children":null,"spread":false},{"title":"KEY.v.bak <span style='color:#111;'> 634B </span>","children":null,"spread":false},{"title":"spwm.v.bak <span style='color:#111;'> 615B </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 2.21KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak10 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak3 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak4 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak5 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak6 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak7 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak8 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA_run_msim_rtl_verilog.do.bak9 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.map.bpm <span style='color:#111;'> 14.69KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.ace_cmp.bpm <span style='color:#111;'> 13.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.cmp.bpm <span style='color:#111;'> 13.90KB </span>","children":null,"spread":false},{"title":"LCD12864_rom_enable.c <span style='color:#111;'> 16.85KB </span>","children":null,"spread":false},{"title":"tm4c123gh6pm_startup_ccs.c <span style='color:#111;'> 14.25KB </span>","children":null,"spread":false},{"title":"tm4c123gh6pz_startup_ccs.c <span style='color:#111;'> 14.25KB </span>","children":null,"spread":false},{"title":"main.c <span style='color:#111;'> 11.07KB </span>","children":null,"spread":false},{"title":"blue.c <span style='color:#111;'> 4.78KB </span>","children":null,"spread":false},{"title":"ADS1118.c <span style='color:#111;'> 3.09KB </span>","children":null,"spread":false},{"title":"bus_fpga.c <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":".ccsproject <span style='color:#111;'> 691B </span>","children":null,"spread":false},{"title":"Tiva TM4C123GH6PM.ccxml <span style='color:#111;'> 1.73KB </span>","children":null,"spread":false},{"title":"Tiva TM4C123GH6PZ.ccxml <span style='color:#111;'> 1.73KB </span>","children":null,"spread":false},{"title":"Tiva TM4C123GH6PGE.ccxml <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.ace_cmp.cdb <span style='color:#111;'> 500.43KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.cmp.cdb <span style='color:#111;'> 500.43KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.map.cdb <span style='color:#111;'> 144.54KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.rtlv_sg.cdb <span style='color:#111;'> 113.92KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.root_partition.cmp.cdb <span style='color:#111;'> 111.49KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.pre_map.cdb <span style='color:#111;'> 108.03KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(4).cnf.cdb <span style='color:#111;'> 100.95KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.root_partition.map.cdb <span style='color:#111;'> 83.61KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autos_3e921.cmp.cdb <span style='color:#111;'> 73.94KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autos_3e921.map.cdb <span style='color:#111;'> 53.40KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(17).cnf.cdb <span style='color:#111;'> 28.88KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(71).cnf.cdb <span style='color:#111;'> 21.08KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(80).cnf.cdb <span style='color:#111;'> 16.95KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autoh_e40e1.cmp.cdb <span style='color:#111;'> 16.79KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(64).cnf.cdb <span style='color:#111;'> 14.61KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.autoh_e40e1.map.cdb <span style='color:#111;'> 14.57KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(21).cnf.cdb <span style='color:#111;'> 12.13KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(15).cnf.cdb <span style='color:#111;'> 11.20KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(26).cnf.cdb <span style='color:#111;'> 10.65KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(0).cnf.cdb <span style='color:#111;'> 9.20KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(8).cnf.cdb <span style='color:#111;'> 7.74KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(16).cnf.cdb <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(5).cnf.cdb <span style='color:#111;'> 6.57KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(22).cnf.cdb <span style='color:#111;'> 6.33KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.rtlv_sg_swap.cdb <span style='color:#111;'> 6.30KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(41).cnf.cdb <span style='color:#111;'> 6.09KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(1).cnf.cdb <span style='color:#111;'> 5.92KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(3).cnf.cdb <span style='color:#111;'> 5.47KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(35).cnf.cdb <span style='color:#111;'> 5.14KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(66).cnf.cdb <span style='color:#111;'> 4.91KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(60).cnf.cdb <span style='color:#111;'> 4.70KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(18).cnf.cdb <span style='color:#111;'> 4.37KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(20).cnf.cdb <span style='color:#111;'> 4.12KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(14).cnf.cdb <span style='color:#111;'> 4.11KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(50).cnf.cdb <span style='color:#111;'> 4.11KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(30).cnf.cdb <span style='color:#111;'> 3.98KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(2).cnf.cdb <span style='color:#111;'> 3.98KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(49).cnf.cdb <span style='color:#111;'> 3.94KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(42).cnf.cdb <span style='color:#111;'> 3.94KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(29).cnf.cdb <span style='color:#111;'> 3.92KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(55).cnf.cdb <span style='color:#111;'> 3.90KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(37).cnf.cdb <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(44).cnf.cdb <span style='color:#111;'> 3.54KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(63).cnf.cdb <span style='color:#111;'> 3.38KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(51).cnf.cdb <span style='color:#111;'> 3.35KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(40).cnf.cdb <span style='color:#111;'> 3.33KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(72).cnf.cdb <span style='color:#111;'> 3.23KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(28).cnf.cdb <span style='color:#111;'> 2.98KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(53).cnf.cdb <span style='color:#111;'> 2.94KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(65).cnf.cdb <span style='color:#111;'> 2.87KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.map_bb.cdb <span style='color:#111;'> 2.77KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(52).cnf.cdb <span style='color:#111;'> 2.76KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(81).cnf.cdb <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(11).cnf.cdb <span style='color:#111;'> 2.51KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(27).cnf.cdb <span style='color:#111;'> 2.47KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(25).cnf.cdb <span style='color:#111;'> 2.47KB </span>","children":null,"spread":false},{"title":"FullBridgeSin-own-FPGA.(75).cnf.cdb <span style='color:#111;'> 2.34KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明