4通道12bit位宽的DA芯片AD5724 Verilog驱动源码+芯片技术手册.zip

4通道12bit位宽的DA芯片AD5724 Verilog驱动源码+芯片技术手册: odule ad5724_ctrl #( parameter DATA_WIDTH = 12 , parameter RANG_WIDTH = 16 )( input wire clk , //这里的时钟频率为50M，如果降低时钟频率请同步降低触发周期i_trig // 提高频率需要代码中o_da5724_sclk的周期 input wire rst_n , input wire i_trig , //DA输出数据更新触发信号，在50M时钟频率下可以设置为5us input wire [DATA_WIDTH - 1 : 0] i_ch1_data , input wire [DATA_WIDTH - 1 : 0] i_ch2_data , input wire [DATA_WIDTH - 1 : 0] i_ch3_data , input wire [DATA_WIDTH - 1 : 0] i_ch4_data , input wire [RANG_WIDTH - 1 : 0] i_out_range , //设置为16'd4 表示输出正负10V input wire i_ad_en , input wire i_da5724_sdout , output wire o_da5724_sclk , output wire o_da5724_sdin , output wire o_da5724_sync_n , output wire o_da5724_ldac_n , output wire o_da5724_clr_n ); localparam POWER_CFG_REF = 24'h10000f ; localparam DV_RANG_CFG_REF = 8'h0c ; localparam CH_A_REF = 8'h00 ; localparam CH_B_REF = 8'h01 ; localparam CH_C_REF = 8'h02 ; localparam CH_D_REF = 8'h03 ; localparam CH_NUM_WIDTH = 2 ; localparam CFG_NUM_WIDTH = 3 ; localparam WAIT_CNT_WIDTH = 4 ; localparam DAC_DATA_WIDTH = 16 ; localparam REG_DATA_WIDTH = 24 ; localparam TRAN_CNT_WIDTH = 5 ; localparam CTRL_ST_WIDTH = 10 ; localparam IDLE = 10'b0000000001 , INIT_PWR = 10'b0000000010 , TRANS_OP_HIGH = 10'b0000000100 , TRANS_OP_LOW = 10'b0000001000 , LDAC_SET = 10'b00000100