EP2C8Q208 RTL8201CL Hub主控板Protel99S设计硬件原理图PCB+BOM+FPGA Verilog源码+设计文档说明.zip

[{"title":"（ 23 个子文件 961KB ） EP2C8Q208 RTL8201CL Hub主控板Protel99S设计硬件原理图PCB+BOM+FPGA Verilog源码+设计文档说明.zip","children":[{"title":"EP2C8Q208_RTL8201CL_(Dual link DVI) Hubprotel硬件原理图+PCB文件+FPGA源码","children":[{"title":"EP2C8Q208_RTL8201CL_(Dual link DVI Hub)-AD版","children":[{"title":"Documents","children":[{"title":"Documents.PrjPcb <span style='color:#111;'> 32.76KB </span>","children":null,"spread":false},{"title":"control.sch <span style='color:#111;'> 6.48KB </span>","children":null,"spread":false},{"title":"VD3030.sch <span style='color:#111;'> 11.50KB </span>","children":null,"spread":false},{"title":"Power.sch <span style='color:#111;'> 24.99KB </span>","children":null,"spread":false},{"title":"FPGA.sch <span style='color:#111;'> 572.50KB </span>","children":null,"spread":false},{"title":"DVI_OUT2.sch <span style='color:#111;'> 26.15KB </span>","children":null,"spread":false},{"title":"memory.sch <span style='color:#111;'> 45.00KB </span>","children":null,"spread":false},{"title":"TQFP64.PCBLIB <span style='color:#111;'> 73.38KB </span>","children":null,"spread":false},{"title":"VD3030.NET <span style='color:#111;'> 33.39KB </span>","children":null,"spread":false},{"title":"DVI_OUT1.sch <span style='color:#111;'> 27.04KB </span>","children":null,"spread":false},{"title":"DVI_IN.sch <span style='color:#111;'> 418.00KB </span>","children":null,"spread":false},{"title":"drive.sch <span style='color:#111;'> 27.06KB </span>","children":null,"spread":false},{"title":"VD3030.PCB <span style='color:#111;'> 1.07MB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"EP2C8Q208_RTL8201CL_(Dual link DVI Hub)电路板原理图设计说明 .doc <span style='color:#111;'> 403.50KB </span>","children":null,"spread":false},{"title":"EP2C8Q208_RTL8201CL_(Dual link DVI Hub)BOM单.xls <span style='color:#111;'> 35.50KB </span>","children":null,"spread":false},{"title":"EP2C8Q208_RTL8201CL_(Dual link DVI Hub).ddb <span style='color:#111;'> 3.60MB </span>","children":null,"spread":false},{"title":"FPGA(EP2C8Q208)-VERILOG逻辑源码","children":[{"title":"clk_lvds.v <span style='color:#111;'> 3.82KB </span>","children":null,"spread":false},{"title":"Led_Ctrl_SV1.v <span style='color:#111;'> 4.22KB </span>","children":null,"spread":false},{"title":"dvi_hub_03.v <span style='color:#111;'> 3.82KB </span>","children":null,"spread":false},{"title":"pll.v <span style='color:#111;'> 8.53KB </span>","children":null,"spread":false},{"title":"clk_test.v <span style='color:#111;'> 2.08KB </span>","children":null,"spread":false},{"title":"dvi_out_02.v <span style='color:#111;'> 10.36KB </span>","children":null,"spread":false},{"title":"crmu_03.v <span style='color:#111;'> 701B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]