FPGA+SDRAM+BCM5421SKQM+RTL8208B千兆百兆以太网主控板protel设计硬件原理图+PCB+FPGA逻辑源码.zip

上传者: GZXGYZ | 上传时间: 2021-03-27 20:19:55 | 文件大小: 1.2MB | 文件类型: ZIP
FPGA+SDRAM+BCM5421SKQM+RTL8208B千兆百兆以太网主控板protel设计硬件原理图+PCB+FPGA逻辑源码,硬件4层板设计,大小为200x150mm,Protel 99se 设计的DDB后缀项目工程文件,包括完整无误的原理图和PCB印制板图,已经在项目中使用,可用Protel或 Altium Designer(AD)软件打开或修改,可作为你产品设计的参考。 核心器件如下: Library Component Count : 41 Name Description ---------------------------------------------------------------------------------------------------- 0006 16PIN 4 HEADER HEADER 4 5208 8 HEADER HEADER 8 93C46 AT24C128 BCM5421S GBIT-CHIP CAP CAP+ CAPACITOR CON2 CON3 Connector CRYSTAL Crystal DSO751S ELECTRO1 Electrolytic Capacitor EP1C6Q240 EPCS1/4 FT245BM HEADER 13X2 HEADER 4X2 HEADER 5X2 HEADER 6 HEADER 8X2 HY57V653220 INDUCTOR INDUCTOR1 JTAG LED LT1086MC MAGNETIC MAGNETIC40 PNP PNP Transistor RES2 RTL8208B SCD_PROGRAMMER SW-PB USB_B ZENER2 配套的cyclone FPGA Verilog源码文件(非工程文件)如下: alt_ram_1024_24.v alt_ram_512_8.v clk_div_80_125.v clk_test.v con1_t_1.v data_test.v data_verify.v init_bcm5421.v init_set.v Led_Ctrl_SV1.v mii_dect.v mii_gen.v mii_man_cnt.v mii_rx.v pll.v pll_inst.v query_link_state.v report_face_t.v RTL8208_test.v rx_t_2.v sdram_addr_test.v sdram_ctrl_05.v sdram_data_test1.v sdram_dqm_test.v sdram_init.v sdram_test_top.v swsr_512_8_dp.v tx_t_1.v usb_ctl.v usb_interface.v usb_phy_rx.v usb_phy_tx.v

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