Altium设计4层板设计 HY57V561620CLT核心板（DDR3菊花链拓扑）原理图PCB工程.zip

[{"title":"（ 16 个子文件 1.1MB ） Altium设计4层板设计 HY57V561620CLT核心板（DDR3菊花链拓扑）原理图PCB工程.zip","children":[{"title":"4层板设计 HY57V561620CLT核心板（菊花链拓扑） SCH+PCB","children":[{"title":"interface.SchDoc <span style='color:#111;'> 288.50KB </span>","children":null,"spread":false},{"title":"4层核心板（菊花链拓扑）.PcbLib <span style='color:#111;'> 689.00KB </span>","children":null,"spread":false},{"title":"CPU.SchDocPreview <span style='color:#111;'> 82.20KB </span>","children":null,"spread":false},{"title":"sdram.SchDoc <span style='color:#111;'> 119.50KB </span>","children":null,"spread":false},{"title":"Mian_CORE（完成版）.PcbDoc.htm <span style='color:#111;'> 5.35KB </span>","children":null,"spread":false},{"title":"CPU.SchDoc <span style='color:#111;'> 134.50KB </span>","children":null,"spread":false},{"title":"flash.SchDoc <span style='color:#111;'> 237.00KB </span>","children":null,"spread":false},{"title":"4层核心板（菊花链拓扑）.PrjPCBStructure <span style='color:#111;'> 45B </span>","children":null,"spread":false},{"title":"interface.SchDocPreview <span style='color:#111;'> 70.71KB </span>","children":null,"spread":false},{"title":"EMC.SchDocPreview <span style='color:#111;'> 57.01KB </span>","children":null,"spread":false},{"title":"4层核心板（菊花链拓扑）.PrjPCB <span style='color:#111;'> 34.83KB </span>","children":null,"spread":false},{"title":"EMC.SchDoc <span style='color:#111;'> 124.00KB </span>","children":null,"spread":false},{"title":"Mian_CORE（完成版）.PcbDoc <span style='color:#111;'> 2.39MB </span>","children":null,"spread":false},{"title":"power.SchDoc <span style='color:#111;'> 230.50KB </span>","children":null,"spread":false},{"title":"Mian_CORE（完成版）.PcbDocPreview <span style='color:#111;'> 97.90KB </span>","children":null,"spread":false},{"title":"flash.SchDocPreview <span style='color:#111;'> 92.34KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]