半整数分频1.5小数分频的功能 FPGA设计Verilog逻辑源码Quartus工程文件.zip
半整数分频1.5小数分频的功能 FPGA设计Verilog逻辑源码Quartus工程文件， Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module div_1_5(clk,div);
input clk; //输入时钟信号
output div; //输出分频信号
reg count; //计数寄存器
reg div; //输出分频寄存器
reg clk_temp2,clk_temp3; //脉冲控制端2寄存器，脉冲控制端3寄存器
assign clk_temp1=clk^clk_temp2; //脉冲控制端1寄存器，等于clk与clk_temp2取异或运算
always@(posedge clk_temp1) //脉冲控制端的上升沿触发
begin
if(count==1'b0) //判断count是否为0，是的话执行以下操作
begin
count<=1'b1; //count置1
clk_temp3<=1'b1; //clk_temp3置1
div<=1'b1; //div置1
end
else //否的话执行以下操作
begin
count<=count-1'b1; //count自减1
clk_temp3<=1'b0; //clk_temp3置0
div<=1'b0; //div置0
end
end
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