串行加法器4位全加器 FPGA设计Verilog逻辑源码Quartus工程文件.zip

上传者: GZXGYZ | 上传时间: 2021-08-24 09:09:20 | 文件大小: 125KB | 文件类型: ZIP
串行加法器4位全加器 FPGA设计Verilog逻辑源码Quartus工程文件, Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module add4(a,b,ci,s,co); input [3:0] a,b; //输入四位数据a,b input ci; //输入进位ci output [3:0] s; //输出四位数据 s output co; //输出进位co assign {co,s}=a+b+ci; //把a、b、ci相加后的结果赋予co、s,其中co放最高位,s放低三位

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