Cyclone4E FPGA设计5位串入并出移位寄存器Verilog逻辑源码Quartus工程文件.zip

上传者: GZXGYZ | 上传时间: 2021-08-23 13:14:09 | 文件大小: 124KB | 文件类型: ZIP
Cyclone4E FPGA设计5位串入并出移位寄存器Verilog逻辑源码Quartus工程文件, Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module reg_cb(clk,din,clr,dout); input clk,din,clr; output[4:0] dout; reg[4:0] dout; always@(posedge clk) begin if(clr) begin dout<=0; end else begin dout<={dout,din}; end

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