模为60的BCD码加法计数器FPGA设计Verilog逻辑源码Quartus工程文件.zip
模为60的BCD码加法计数器FPGA设计Verilog逻辑源码Quartus工程文件， Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module cnt_60(clk,reset,cin,load,data,cout,qout);
input clk,reset,cin,load; //输入时钟，复位，计数端，置数端
input[7:0] data; //预置数输入端
output cout; //输出进位信号端
output[7:0] qout; //计数输出端
reg[7:0] qout; //计数输出端寄存器
always@(posedge clk) //时钟上升沿触发
begin
if(reset) //判断是否复位信号端为1
qout<=0; //计数输出端置0
else if(load) //判断置数端是否有效
qout<=data; //将预置数输入端数据赋予计数输出寄存器
else if(cin) //判断计数端是否有效
begin
if(qout[3:0]==9) //判断qout的低位是否为9
begin
qout[3:0]<=0; //qout低位清0
if(qout[7:4]==5) //判断qout高位是否为5
qout[7:4]<=0; //qout高位清0
else
qout[7:4]<=qout[7:4]+4'b1; //高位自加1
end
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