同步十位减法计数器Cyclone4E FPGA设计Verilog逻辑源码Quartus工程文件.zip

上传者: GZXGYZ | 上传时间: 2021-08-23 13:13:56 | 文件大小: 124KB | 文件类型: ZIP
同步十位减法计数器Cyclone4E FPGA设计Verilog逻辑源码Quartus工程文件, Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module cnt_jf(clk,rst,q); input clk; //输入时钟 input rst; //输入复位信号,高电平有效 output[3:0] q; //输出计数端 reg[3:0] q; //输出计数端寄存器 always@(posedge clk) //时钟上升沿触发 begin if(rst) //判断rst是否有效 begin q<=0; //q清零 end else if(q==4'b0000) //q是否等于0 begin q<=4'b1001; //q置9 end else begin q<=q-4'b1; //q自减1

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