[{"title":"( 62 个子文件 124KB ) 同步十位减法计数器Cyclone4E FPGA设计Verilog逻辑源码Quartus工程文件.zip","children":[{"title":"减法计数器","children":[{"title":"cnt_jf_assignment_defaults.qdf <span style='color:#111;'> 47.23KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"cnt_jf.hif <span style='color:#111;'> 768B </span>","children":null,"spread":false},{"title":"cnt_jf.sgdiff.hdb <span style='color:#111;'> 8.70KB </span>","children":null,"spread":false},{"title":"cnt_jf.cmp_merge.kpt <span style='color:#111;'> 215B </span>","children":null,"spread":false},{"title":"cnt_jf.smart_action.txt <span style='color:#111;'> 5B </span>","children":null,"spread":false},{"title":"cnt_jf.cmp.rdb <span style='color:#111;'> 4.95KB </span>","children":null,"spread":false},{"title":"prev_cmp_cnt_jf.qmsg <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false},{"title":"cnt_jf.rtlv_sg_swap.cdb <span style='color:#111;'> 192B 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