Cyclone4E FPGA设计4位并入串出移位寄存器Verilog逻辑源码Quartus工程文件.zip

[{"title":"（ 61 个子文件 128KB ） Cyclone4E FPGA设计4位并入串出移位寄存器Verilog逻辑源码Quartus工程文件.zip","children":[{"title":"4位并入串出移位寄存器","children":[{"title":"reg_bc.v <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"reg_bc.qsf <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"reg_bc.sim.cvwf <span style='color:#111;'> 939B </span>","children":null,"spread":false},{"title":"reg_bc.rtlv_sg_swap.cdb <span style='color:#111;'> 192B </span>","children":null,"spread":false},{"title":"prev_cmp_reg_bc.map.qmsg <span style='color:#111;'> 3.63KB </span>","children":null,"spread":false},{"title":"reg_bc.map.kpt <span style='color:#111;'> 453B </span>","children":null,"spread":false},{"title":"reg_bc.cmp_merge.kpt <span style='color:#111;'> 211B </span>","children":null,"spread":false},{"title":"reg_bc.sld_design_entry.sci <span style='color:#111;'> 212B </span>","children":null,"spread":false},{"title":"reg_bc.map.hdb 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