同步24进制计数器FPGA设计Verilog逻辑源码Quartus工程文件.zip
同步24进制计数器FPGA设计Verilog逻辑源码Quartus工程文件， Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module cnt_24(ten,one,co,clk,clr);
input clk; //输入时钟
input clr; //清零输入端
output co; //进位输出端
output[3:0] ten,one; //十位输出，个位输出
reg co; //进位输出端寄存器
reg[3:0] ten,one; //十位输出寄存器，个位输出寄存器
always@(posedge clk) //时钟上升沿触发
begin
if(clr) //判断清零信号是否有效，即为1
begin
ten<=0; //十位清零
one<=0; //个位清零
end
else
begin
if({ten,one}==8'b00100011) //判断是否计数到23
begin
ten<=0; //十位清零
one<=0; //个位清零
co<=1; //进位置1
end
else if(one==4'b1001) //判断各位是否为9
begin
one<=0; //是的话个位置0
ten<=ten+4'b1; //十位自加1
co<=0; //进位置0
end
else
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