基于FPGA设计的SD卡音乐播放Verilog逻辑源码Quartus工程文件+文档说明.zip

基于FPGA设计的SD卡音乐播放Verilog逻辑源码Quartus工程文件+文档说明，音频编解码芯片选用WOLFSON 公司的 WM8731 芯，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input key1, input wm8731_bclk, //audio bit clock input wm8731_daclrc, //DAC sample rate left right clock output wm8731_dacdat, //DAC audio data output input wm8731_adclrc, //ADC sample rate left right clock input wm8731_adcdat, //ADC audio data input inout wm8731_scl, //I2C clock inout wm8731_sda, //I2C data output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output [5:0] seg_sel, output [7:0] seg_data ); wire[9:0] lut_index; wire[31:0] lut_data; wire[3:0] state_code; wire[6:0] seg_data_0; //I2C master controller i2c_config i2c_config_m0( .rst (~rst_n ), .clk (clk ), .clk_div_cnt (16'd99 ), .i2c_addr_2byte (1'b0 ), .lut_index (lut_index ), .lut_dev_addr (lut_data[31:24] ), .lut_reg_addr (lut_data[23:8] ), .lut_reg_data (lut_data[7:0] ), .error ( ), .done ( ), .i2c_scl