FPGA 读写i2c_eeprom_Verilog逻辑源码Quartus工程文件+文档说明.zip

FPGA 读写i2c_eeprom_Verilog逻辑源码Quartus工程文件+文档说明，EEPROM 型号24LC04,，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module i2c_eeprom_test( input clk, input rst_n, input key1, inout i2c_sda, inout i2c_scl, output [5:0] seg_sel, output [7:0] seg_data ); localparam S_IDLE = 0; localparam S_READ = 1; localparam S_WAIT = 2; localparam S_WRITE = 3; reg[3:0] state; wire button_negedge; reg[7:0] read_data; reg[31:0] timer; wire scl_pad_i; wire scl_pad_o; wire scl_padoen_o; wire sda_pad_i; wire sda_pad_o; wire sda_padoen_o; reg[ 7:0] i2c_slave_dev_addr; reg[15:0] i2c_slave_reg_addr; reg[ 7:0] i2c_write_data; reg i2c_read_req; wire i2c_read_req_ack; reg i2c_write_req; wire i2c_write_req_ack; wire[7:0] i2c_read_data; ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key1), .button_posedge (), .button_negedge (button_negedge), .button_out () ); wire[6:0] seg_data_0; seg_decoder seg_decoder_m0( .bin_data (read_data[3:0]), .seg_data (seg_data_0) ); wire[6:0] seg_data_1; seg_decoder seg_decoder_m1( .bin_data (read_data[7:4]), .seg_data (seg_data_1) ); seg_scan seg_scan_m0( .clk (clk), .rst_n (rst_n), .seg_sel (seg_sel), .seg_data (seg_data), .seg_data_0 ({1'b1,7'b1111_111}), .seg_data_1 ({1'b1,7'b1111_111}), .seg_data_2 ({1'b1,7'b1111_111}), .seg_data_3 ({1'b1,7'b1111_111}), .seg_data_4 ({1'b1,seg_data_1}), .seg_data_5 ({1'b1,seg_data_0}) ); always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin state <= S_IDLE; i2c_write_req <= 1'b0; read_data <= 8'h00; timer <= 32'd0; i2c_write_data <= 8'd0; i2c_slave_reg_addr <= 16'd0; i2c_slave_dev_addr <= 8'ha0;//1010 000 0(default address ‘000’ write operation) i2c_read_req <= 1'b0; en