EPM240 CPLD开发板Verilog HDL设计SRAM读写Quartus 13.1工程密码+设计说明文档.zip

上传者: GJZGRB | 上传时间: 2021-03-31 16:08:05 | 文件大小: 459KB | 文件类型: ZIP
EPM240 CPLD开发板Verilog HDL设计SRAM读写Quartus 13.1工程密码+设计说明文档。SRAM 芯片时序操作大同小异,在这里总结一些它们共性的东西,也提一些用 Verilog 简单的快速操作 SRAM 的技巧。 这里就以本实验使用的 IS62LV256-70U 为例进行说明。其管脚定义如表 5.18 所示。 表 5.18 SRAM 管脚定义 序号 管脚 描述 1 A0-A14 地址输入。 2 CEn 芯片使能输入,低有效。 3 OEn 输出使能输入,低有效。 4 WEn 写使能输入,低有效。 5 I/O0-I/O7 数据输入/输出。 6 VCC 电源。 7 GND 数字地。 具体在硬件连接的时候,其实很多人喜欢直接把输出使能信号 OEn 和片选信号 CEn 接 地,这样一来不仅节省了处理器和 SRAM 连接的管脚数,而且在读写 SRAM 的时候其实只要 对写使能信号 WEn 操作就可以了,简化了代码部分。本设计的硬件原理图如图 5.23 所示。 图 5.23 SRAM 接口 因为在硬件上已经把 CEn 和 OEn 拉低了,所以在不进行写 SRAM 的时候,实际上 SRAM 的数据总线上的值是对应地址总线的数据。为了避免误操作,可以把地址总线置高阻态,如 果不去操作数据总线(最好不是复用的数据总线)也无大碍。因为这样简化了设计。对于 SRAM 的操作时序,只要关心地址总线、数据总线和写使能 WEn 信号。读写时序分别如图 5.24 和图 5.25 所示。

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