EPM240 CPLD UART串口通信verilog Quartus ii 工程源码.zip
EPM240 CPLD UART串口通信 verilog Quartus ii 工程源码, 逻辑芯片为EPM240T100C5, quartus ii 10.1逻辑源码工程文件，
verilog上电蜂鸣器响一声，3个LED灯闪烁，然后串口数据收发，串口波特率11520，1起始位8数据位1停止位，数据通信协议：发送55 F1 01 (DATA) FF 32路GPIO中的一路输出高，接收数据返回： AA AA BB CC DD
完整的quartus ii 10.1工程文件，可以做为你的设计参考。
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