Xilinx FPGA XC7Z020CLG400 USB3320 RTL8211 AD设计核心板原理图+pcb文件.zip

[{"title":"（ 24 个子文件 1.19MB ） Xilinx FPGA XC7Z020CLG400 USB3320 RTL8211 AD设计核心板原理图+pcb文件.zip","children":[{"title":"PCB_Project1.PrjPCBStructure <span style='color:#111;'> 48B </span>","children":null,"spread":false},{"title":"SYS-PS.SchDoc <span style='color:#111;'> 139.50KB </span>","children":null,"spread":false},{"title":"ZYNQ400-MIO.SchDocPreview <span style='color:#111;'> 94.76KB </span>","children":null,"spread":false},{"title":"ZYNQ400-CONDIP.SchDocPreview <span style='color:#111;'> 42.83KB </span>","children":null,"spread":false},{"title":"PCB_Project1.PrjPCB <span style='color:#111;'> 32.84KB </span>","children":null,"spread":false},{"title":"ZYNQ400-MIO.SchDoc <span style='color:#111;'> 640.50KB </span>","children":null,"spread":false},{"title":"PCB.PcbDocPreview <span style='color:#111;'> 69.03KB </span>","children":null,"spread":false},{"title":"ZYNQ400-CONFPC.SchDocPreview <span style='color:#111;'> 78.40KB </span>","children":null,"spread":false},{"title":"ZYNQ400-DDR.SchDocPreview <span style='color:#111;'> 135.23KB </span>","children":null,"spread":false},{"title":"PCB.PcbLib <span style='color:#111;'> 200.00KB </span>","children":null,"spread":false},{"title":"ZYNQ400-ETH.SchDocPreview <span style='color:#111;'> 51.79KB </span>","children":null,"spread":false},{"title":"ZYNQ400-EMIO.SchDoc <span style='color:#111;'> 614.50KB </span>","children":null,"spread":false},{"title":"SYS-PS.SchDocPreview <span style='color:#111;'> 60.35KB </span>","children":null,"spread":false},{"title":"ZYNQ400-POWER.SchDoc <span style='color:#111;'> 391.50KB </span>","children":null,"spread":false},{"title":"ZYNQ400-CONFPC.SchDoc <span style='color:#111;'> 267.50KB </span>","children":null,"spread":false},{"title":"ZYNQ400-POWER.SchDocPreview <span style='color:#111;'> 40.06KB </span>","children":null,"spread":false},{"title":"ZYNQ400-EMIO.SchDocPreview <span style='color:#111;'> 100.84KB </span>","children":null,"spread":false},{"title":"ZYNQ400-USB.SchDoc <span style='color:#111;'> 70.00KB </span>","children":null,"spread":false},{"title":"ZYNQ400-ETH.SchDoc <span style='color:#111;'> 140.50KB </span>","children":null,"spread":false},{"title":"ZYNQ400-CONDIP.SchDoc <span style='color:#111;'> 100.50KB </span>","children":null,"spread":false},{"title":"PCB.PcbDoc.htm <span style='color:#111;'> 4.97KB </span>","children":null,"spread":false},{"title":"ZYNQ400-DDR.SchDoc <span style='color:#111;'> 469.50KB </span>","children":null,"spread":false},{"title":"PCB.PcbDoc <span style='color:#111;'> 2.89MB </span>","children":null,"spread":false},{"title":"ZYNQ400-USB.SchDocPreview <span style='color:#111;'> 38.08KB </span>","children":null,"spread":false}],"spread":true}]