基于FPGA硬件平台实现的高效数字信号处理系统_采用VerilogHDL硬件描述语言设计的可配置参数FIR数字滤波器_支持多种窗函数选择与实时信号处理_包含系数生成模块数据缓冲模.zip

[{"title":"（ 28 个子文件 5.88MB ） 基于FPGA硬件平台实现的高效数字信号处理系统_采用VerilogHDL硬件描述语言设计的可配置参数FIR数字滤波器_支持多种窗函数选择与实时信号处理_包含系数生成模块数据缓冲模.zip","children":[{"title":"FIR-filter-based-on-the-FPGA-main","children":[{"title":"FIR_FILTER_simulation.asv <span style='color:#111;'> 1.94KB </span>","children":null,"spread":false},{"title":"hamming_2_25_25.xco <span style='color:#111;'> 3.04KB </span>","children":null,"spread":false},{"title":"002.BMP <span style='color:#111;'> 25.65KB </span>","children":null,"spread":false},{"title":"FIR_FILTER_simulation.m <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"rom_ctrl.v <span style='color:#111;'> 1.70KB </span>","children":null,"spread":false},{"title":"001.BMP <span style='color:#111;'> 24.64KB </span>","children":null,"spread":false},{"title":"001.fda <span style='color:#111;'> 25.09KB </span>","children":null,"spread":false},{"title":"HAMMING_2_25_50.xco <span style='color:#111;'> 3.04KB </span>","children":null,"spread":false},{"title":"hamming_2_25_25.coe <span style='color:#111;'> 375B </span>","children":null,"spread":false},{"title":"HAMMING_2_25_50.coe <span style='color:#111;'> 525B </span>","children":null,"spread":false},{"title":"key.v <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"hamming_2_25_25_8.coe <span style='color:#111;'> 375B </span>","children":null,"spread":false},{"title":"FIR_SIN.xise <span style='color:#111;'> 6.22KB </span>","children":null,"spread":false},{"title":"HAMMING_2_25_50.v <span style='color:#111;'> 606.78KB </span>","children":null,"spread":false},{"title":"AD.v <span style='color:#111;'> 842B </span>","children":null,"spread":false},{"title":"HAMMING_2_25_50.fda <span style='color:#111;'> 5.30KB </span>","children":null,"spread":false},{"title":"untitled.fda <span style='color:#111;'> 5.20KB </span>","children":null,"spread":false},{"title":"FIR_LPF.v <span style='color:#111;'> 8.12KB </span>","children":null,"spread":false},{"title":"hamming_2_25_25.v <span style='color:#111;'> 365.08KB </span>","children":null,"spread":false},{"title":"rom_addr.v <span style='color:#111;'> 808B </span>","children":null,"spread":false},{"title":"SIN.ucf <span style='color:#111;'> 2.04KB </span>","children":null,"spread":false},{"title":"基于FPGA的FIR低通滤波器设计总结报告.docx <span style='color:#111;'> 2.71MB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 57B </span>","children":null,"spread":false},{"title":"2_32.fda <span style='color:#111;'> 5.39KB </span>","children":null,"spread":false},{"title":"DAC_CTR.v <span style='color:#111;'> 831B </span>","children":null,"spread":false},{"title":"基于FPGA的FIR低通滤波器设计总结报告.pdf <span style='color:#111;'> 4.10MB </span>","children":null,"spread":false}],"spread":false},{"title":"说明文件.txt <span style='color:#111;'> 873B </span>","children":null,"spread":false},{"title":"附赠资源.docx <span style='color:#111;'> 41.95KB </span>","children":null,"spread":false}],"spread":true}]