PWM信号发生器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Pwm is port(
clk: in std_logic; --clk signal
wr_n:in std_logic; --write signal
addr:in std_logic; --address signal
WrData:in std_logic_vector(7 downto 0); --writedata signal
PwmOut:out std_logic); --Global signal
end Pwm;
architecture one of Pwm is
signal period:std_logic_vector(7 downto 0);
signal duty:std_logic_vector(7 downto 0);
signal counter:std_logic_vector(7 downto 0);
Begin
process(clk,WrData)
begin
if rising_edge(clk) then
if (wr_n='0') then
if addr='0' then
period<=WrData; duty<=duty;
else period<=period; duty<=WrData;
end if;
else
period<=period; duty<=duty;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if counter=0 then
counter<=period;
else
counter<=counter-1;
end if;
if counter>duty then
PwmOut<='0';
else PwmOut<='1';
end if;
end if;
end process;
end one;
2022-06-19 14:28:17
20.91MB
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