7 Series Integrated Block for PCIe (v1.7)，有关PCIE IP核的使用

pg054-7series-pcie 官方资料 对PCIe编程爱好者具有参考和借鉴意义。

PCI 是外围设备互连（Peripheral Component Interconnect）的简称，作为一种通用的 总线接口标准，它在目前的计算机系统中得到了非常广泛的应用。PCI 提供了一组完整的 总线接口规范，其目的是描述如何将计算机系统中的外围设备以一种结构化和可控化的方 式连接在一起，同时它还刻画了外围设备在连接时的电气特性和行为规约，并且详细定义 了计算机系统中的各个不同部件之间应该如何正确地进行交互。

This paper presents power management guidelines for PCI Express links on Intel-based Mobile platforms. It describes the mapping from platform sleeping states and device power states to link power states, including the procedure to support Mobile-specific S1/POS and CPU C3/C4 scenarios. Device and platform power saving opportunities are identified for each link power state. L1 entry policy is also recommended to optimize device power. Several power optimization techniques are described, including minimizing flow control updates and acknowledgement packets to improve bandwidth efficiency, and pipelining packets to increase opportunities for active state link power management. These power management guidelines enable architectural innovation to achieve power-optimized interconnect performance.

PCI Express规范、协议介绍，最新版（V3.0）,设计PCIE板卡的时候找到的资料，有PCIE接口介绍、信号介绍以及电气特性介绍、以及PCIE板卡连接器规范介绍等。

pcie dma 官方驱动源码

1. INTRODUCTION............................................................................................................... 46 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50 1.3.1. Root Complex........................................................................................................ 50 1.3.2. Endpoints .............................................................................................................. 51 1.3.3. Switch .................................................................................................................... 54 1.3.4. Root Complex Event Collector .............................................................................. 55 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 55 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 56 1.5.1. Transaction Layer ................................................................................................. 57 1.5.2. Data Link Layer .................................................................................................... 57 1.5.3. Physical Layer ...................................................................................................... 58 1.5.4. Layer Functions and Services............................................................................... 58 TRANSACTION LAYER SPECIFICATION ................................................................. 62 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 62 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 63 2.1.2. Packet Format Overview ...................................................................................... 65 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 67 2.2.1. Common Packet Header Fields ............................................................................ 67 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.3. TLP Digest Rules .................................................................................................. 74 2.2.4. Routing and Addressing Rules .............................................................................. 74 2.2.5. First/Last DW Byte Enables Rules........................................................................ 78 2.2.6. Transaction Descriptor ......................................................................................... 81 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 87 2.2.8. Message Request Rules ......................................................................................... 94 2.2.9. Completion Rules ................................................................................................ 115 2.2.10. TLP Prefix Rules ................................................................................................. 118 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 123 2.3.1. Request Handling Rules...................................................................................... 126 2.3.2. Completion Handling Rules................................................................................ 138 2.4. TRANSACTION ORDERING ............................................................................................ 142 2.4.1. Transaction Ordering Rules ............................................................................... 142 ......

xilinx pcie ip 英文版资料

'We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others.' --Nader Saleh, CEO/President, Catalyst Enterprises, Inc. PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnect

基于petalinux+vivado的zcu102 demo板的PS端PCIE接口配置与调试经验，包括vivado设置pcie的ip核和petalinux配置设备树及linux内核/根文件系统，已经相关lspci工具的测试。