7 Series Integrated Block for PCIe (v1.7)，有关PCIE IP核的使用

基于FPGA的PCI总线从接口IP核的设计与实现

基于PC的虚拟总线驱动开发 实现了 pxl9054硬件DMA驱动 wdm实现 虚拟总线程序

fpga开发pci的verilog，不可多得的源代码。

'We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others.' --Nader Saleh, CEO/President, Catalyst Enterprises, Inc. PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnects, PCI Express provides significantly higher performance, reliability, and enhanced capabilities--at a lower cost--than the previous PCI and PCI-X standards. Therefore, anyone working on next-generation PC systems, BIOS and device driver development, and peripheral device design will need to have a thorough understanding of PCI Express. PCI Express System Architecture provides an in-depth description and comprehensive reference to the PCI Express standard. The book contains information needed for design, verification, and test, as well as background information essential for writing low-level BIOS and device drivers.In addition, it offers valuable insight into the technology's evolution and cutting-edge features. Following an overview of the PCI Express architecture, the book moves on to cover transaction protocols, the physical/electrical layer, power management, configuration, and more. Specific topics covered include: *Split transaction protocol *Packet format and definition, including use of each field *ACK/NAK protocol *Traffic Class and Virtual Channel applications and use *Flow control initialization and operation *Error checking mechanisms and reporting options *Switch design issues *Advanced Power Management mechanisms and use *Active State Link power management *Hot Plug design and operation *Message transactions *Physical layer functions *Electrical signaling characteristics and issues *PCI Express enumeration procedures *Configuration register definitions Thoughtfully organized, featuring a plethora of illustrations, and comprehensive in scope, PCI Express System Architecture is an essential resource for anyone working with this important technology.MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. 0321156307B08262003

This paper presents power management guidelines for PCI Express links on Intel-based Mobile platforms. It describes the mapping from platform sleeping states and device power states to link power states, including the procedure to support Mobile-specific S1/POS and CPU C3/C4 scenarios. Device and platform power saving opportunities are identified for each link power state. L1 entry policy is also recommended to optimize device power. Several power optimization techniques are described, including minimizing flow control updates and acknowledgement packets to improve bandwidth efficiency, and pipelining packets to increase opportunities for active state link power management. These power management guidelines enable architectural innovation to achieve power-optimized interconnect performance.

PCI Express Base Specification Revision 2.0 协议规范

PCI Express规范、协议介绍，最新版（V3.0）,设计PCIE板卡的时候找到的资料，有PCIE接口介绍、信号介绍以及电气特性介绍、以及PCIE板卡连接器规范介绍等。

pci local bus specification2.2 ，包含目录结构

1. INTRODUCTION............................................................................................................... 46 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50 1.3.1. Root Complex........................................................................................................ 50 1.3.2. Endpoints .............................................................................................................. 51 1.3.3. Switch .................................................................................................................... 54 1.3.4. Root Complex Event Collector .............................................................................. 55 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 55 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 56 1.5.1. Transaction Layer ................................................................................................. 57 1.5.2. Data Link Layer .................................................................................................... 57 1.5.3. Physical Layer ...................................................................................................... 58 1.5.4. Layer Functions and Services............................................................................... 58 TRANSACTION LAYER SPECIFICATION ................................................................. 62 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 62 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 63 2.1.2. Packet Format Overview ...................................................................................... 65 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 67 2.2.1. Common Packet Header Fields ............................................................................ 67 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.3. TLP Digest Rules .................................................................................................. 74 2.2.4. Routing and Addressing Rules .............................................................................. 74 2.2.5. First/Last DW Byte Enables Rules........................................................................ 78 2.2.6. Transaction Descriptor ......................................................................................... 81 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 87 2.2.8. Message Request Rules ......................................................................................... 94 2.2.9. Completion Rules ................................................................................................ 115 2.2.10. TLP Prefix Rules ................................................................................................. 118 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 123 2.3.1. Request Handling Rules...................................................................................... 126 2.3.2. Completion Handling Rules................................................................................ 138 2.4. TRANSACTION ORDERING ............................................................................................ 142 2.4.1. Transaction Ordering Rules ............................................................................... 142 ......