PICMG_EXP.0_R1.0_Specificaion
Contents
Introduction
1.1 Statement of Compliance 13
1.2 Terminology 13
1.3 Applicable Documents 18
1.4 Objectives …19
1.5 Name and Logo Usage....20
1.5.1 Logo Use 20
1.5.2 Trademark polic 20
1.6 Intellectual Property 21
1.7 Special Word Usage 22
1.8 Connectors
1.8.1 Legacy CompactPCI Connectors 22
1.8.2 High -Speed Advanced differential Fabric Connectors
1.83 UPM Power Connectors∴… 25
1.8.3.1 System Slot/Board and Type 1 Peripheral Slot/Board .25
1.8.3.2 Switch Slot/ Board 26
1.8.4 eHM C 27
1.8.5 CompactPCI Pluggable Power Supply Connector 27
1.9 Slot and board descriptions 28
1.9.1 Connector Reference Designators...............31
1.9.2 System Slot and Board
1.9.3 Type 1 Peripheral Slot and Board 32
1.9.4 Type 2 Peripheral Slot and Board 33
1.9.5 Hybrid Peripheral slot 35
1.9.6 Legacy Slot
1.9.7 Switch Slot and board .36
197.13uSwitchSlotandboard.36
1.9.7.2 6U Switch Slot and board 37
1.10 EXample Configurations 40
2 Mechanical Requirements 45
2.1 Mechanical Overview 45
2.2 Dray
Standard 45
2.3 Units 45
2.4 Keepout Zones 45
2.5 Connector Requirements .45
2.5.1 ADF Connectors 45
2.5.1.1 Board connectors 45
2.5.1.3 Backplane Connectors with Hot-Plug Support
2.5.1.2 Backplane Connectors without Hot-Plug Support 46
2.5.2 eHM Connectors 46
2.5.2.1 Board Connector Type Designation .46
2.5.2.2 Backplane Connectors without Hot-Plug Support .........46
2.5.2.3 Backplane Connectors with Hot-Plug Support..... 46
2.5.3 UPM Connectors 46
2.5.3.1 Backplane connectors 46
2.5.3.2 Board Connectors without Hot-Plug Support 47
2.5.3.3 Board Connectors with Hot-Plug Support
2.5.4 HM Conne 47
2.5.5 47-Position Pluggable Power Supply Connector 47
2.6 Chassis Subrack Requirements 47
2.7 Backplane Requirements 47
2.7.1 3U Backplane Dimensions and Connector Locations....... 47
2.7.2 6U Backplane Dimensions and Connector Locations
2.8 Slot Numbering and Glyphs 51
2.9 Board Requirements .51
2.9.1 3U System/Type 1/Type 2 Board Dimensions and Connector Locations 51
2.9.2 6U System/Type 1/Type 2 Board Dimensions and Connector Locations
2.9.3 3U Switch board dimensions and connector locations wwm . 54
29.4 6U Switch board dimensions and connector locations .55
2.9.5 Board pcb thickness 56
2.9.6 ESD Discharge Strip 56
2.9.7 ESD Clip 56
2.9.8 Front Panels 56
2.9.9 CompactPcI Express logo 57
2.9.10 PMC/XMC Support ….57
29.11 Cross sectional vi 58
2.9.12 Component Outline and Warpage 58
2.9.13 Solder Side Cover(Optional) 58
2. 9.14 Component Heights
2.9. 15 System Slot Identification 59
2.10 Rear-Panel 1/0 Board Requirements 59
2.10.1 3U Rear-Panel l/o board dimensions 59
2.10.2 6U Rear-Panel l/o board dimensions
3 Electrical Requirements 62
3. 1 Signal Definitions 62
3.1.1 PCI Express Signals .62
3.1.1.1 PCI EXpress Transmit SigInaIs
3.1.1.2 PCI Express Receive Signals 62
3.1.1.3 Interconnect Definition 63
3.1.1.3.1 Link definit 63
3.1.1.3.2 Link Grouping .63
3.1.1.4 Electrical B 64
3. 1.1.4.1 AC Coupling 65
3.1.1.4.2 Insertion loss 65
3.1.1.4.3 Crosstab‖k
3.1.1.4,4 Lane-to-Lane skew
3.1.1.4.5 Equalization…….….………..…..67
3.1.1.4.6 Skew within the Differential Pair(Intra-Pair Skew)
3.1.1.5 Jitter Budget Allocation 68
3.1.1.5. 1 Random Jitter(Rj) 68
3.1.1.5.2 System Level Jitter Distribution 69
3.1.1.5.3 Interconnect Jitter Budget 69
3.1.1.5. 4 Eye Patterns 70
3.1.1.5.5 Type 2 Peripheral Transmitter Eye
3.1.1.5.6 Controller Transmitter Eye
3.1.1.5.7 Type 2 Peripheral Receiver Eye
3.1.1.5. 8 Controller Receiver eye 74
3.1.1.5. 9 Backplane Compliance Testing
3.1.1.5. 10 Alternative Controller tX measurement.wm .77
3.1.1.6 Reference Clock 78
3.1.1.6.1Hot-Pug…...….78
3.1.1.6.2 Clock Fan-Out ..79
3. 1.1.6.3 Clocking dependencies
3. 1.1.6.4 AC-Coupling and Biasing 79
3.1.1.6.5 Routing length 80
3. 1.1.6.6 Reference Clock Specification 81
3.1.1.6.7 REFCLK Phase Jitter Specification
3.1.2ESD 85
3.1.35VauX. 85
3.1.4 SMBI
3.1.4.1 SMBus " Back Powering Considerations 88
3.1.4.2 Backplane Identification and Capability Using SMBus . 88
3.1.5 PWRBTN# Signal 94
3.1.6 PS ON# Signal .94
3.1.7 PWR OK Signal.......95
3.1.8 WAKE# Signal
3.1.8. 1 Implementation Note 98
3.1. 9 PERST# Signal 99
3.1.9.1 nitial Power-Up(G3toL0)……………………100
3.1.9.2 Power Management States(so to S3/S4 to so) 101
3.1.9.3 Power down 102
3.1.10 SYSEN# Signal… 103
3.1.11 Geographical Addressing 103
3. 1. 12 LINKCAP Signal 104
3.1.13/OPin 104
3.1.14 Reserved pins 104
3.2 Hot-Plug Support .104
3.2.1 Hot-Plug sub-System Architecture 104
3.2.2 Power enable 107
3.2.3 Wake# 108
3.2.4 Module Power good 108
3.2.5 Present detection 108
3.2.6 System Management Bus 108
3.2.7 System Management Bus alert 108
3.2.8 Attention LED 109
3.2.9 Attention
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