verilog程序设计实例学习基础教程FPGA教学实验Verilog HDL例程源码合集:
accn.v
account.v
add4_1.v
add4_2.v
add4_3.v
add8.v
add8_tp.v
adder.v
adder16.v
adder4.acf
adder4.hif
adder4.ndb
adder4.v
adder8.v
adder_tp.v
add_ahead.v
add_bx.v
add_jl.v
add_tree.v
alu.v
alutask.v
alu_tp.v
aoi.v
bidir.v
bidir2.v
block.v
block1.v
block2.v
block3.v
block4.v
buried_ff.v
carry_udp.v
carry_udpx1.v
carry_udpx2.v
clock.v
code_83.v
compile.v
control.v
correlator.v
count.v
count10.v
count4.v
count4_tp.v
count60.v
count8_tp.v
crc.v
cycle.v
decode47.v
decode4_7.v
decoder1.v
decoder2.v
decoder_38.v
delay.v
dff.v
dff1.v
dff2.v
dff_udp.v
encoder8_3.v
examples.pdf
fir.v
fre_ctrl.v
fsm.v
full_add1.v
full_add2.v
full_add3.v
full_add4.v
full_add5.v
funct.v
funct_tp.v
gate1.v
gate2.v
gate3.v
half_add1.v
half_add2.v
half_add3.v
half_add4.v
jk_ff.v
johnson.v
latch.v
latch_1.v
latch_16.v
latch_2.v
latch_8.v
linear.v
longframe1.v
longframe2.v
loop1.v
loop2.v
loop3.v
mac.v
mac_tp.v
map_lpm_ram.v
mpc.v
mpc_tp.v
mult.v
mult4x4.v
mult_for.v
mult_repeat.v
mult_tp.v
mux21_1.v
mux21_2.v
mux2_1a.v
mux2_1b.v
mux2_1c.v
mux31.v
mux4_1.v
mux4_1a.v
mux4_1b.v
mux4_1c.v
mux4_1d.v
mux_case.v
mux_casez.v
mux_if.v
mux_tp.v
non_block.v
paobiao.v
paral1.v
paral2.v
parity.v
pipeline.v
ram256x8.v
random_tp.v
reg8.v
resource1.v
resource2.v
rom.v
sell.v
serial1.v
serial2.v
serial_pal.v
shifter.v
song.v
test.v
test1.v
test2.v
time_dif.v
traffic.v
transcript
tri_1.v
tri_2.v
updown_count.v
voter7.v
wave1.v
wave2.v
2021-03-23 18:10:31
176KB