V7-057_ AD7606的FMC DMA双缓冲总线驱动方式实现
2021-05-01 09:01:56
13.88MB
1
int main(void)
{
//System Clocks Configuration
SystemInit();
SCL_IO_Init();
SCL_SPI_Init();
//CAN Configuration
SCL_CAN_Init();
EXIT_Configuration();
SCL_IO_DefaultValue();
SCL_TIMEX_Init();
// ADC_Configuration();
// GPIO_SetBits(GPIOD,GPIO_Pin_0);//CS_0();
// GPIO_SetBits(GPIOD,GPIO_Pin_1);//CS_0();
// GPIO_SetBits(GPIOE,GPIO_Pin_5);//CS_0();
while(1)
{
}
}
2021-04-29 11:11:30
21.48MB
1
F4-029_AD7606数据采集模块例程（For STM32F407)
2021-04-17 15:13:26
2.72MB
1
FPGA读取模数转换芯片AD7606数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。
module top(
input clk,
input rst_n,
input[15:0] ad7606_data, //ad7606 data
input ad7606_busy, //ad7606 busy
input ad7606_first_data, //ad7606 first data
output[2:0] ad7606_os, //ad7606
output ad7606_cs, //ad7606 AD cs
output ad7606_rd, //ad7606 AD data read
output ad7606_reset, //ad7606 AD reset
output ad7606_convstab, //ad7606 AD convert start
//vga output
output vga_out_hs, //vga horizontal synchronization
output vga_out_vs, //vga vertical synchronization
output[4:0] vga_out_r, //vga red
output[5:0] vga_out_g, //vga green
output[4:0] vga_out_b //vga blue
);
wire video_clk;
wire video_hs;
wire video_vs;
wire video_de;
wire[7:0] video_r;
wire[7:0] video_g;
wire[7:0] video_b;
wire grid_hs;
wire grid_vs;
wire grid_de;
wire[7:0] grid_r;
wire[7:0] grid_g;
wire[7:0] grid_b;
wire wave0_hs;
wire wave0_vs;
wire wave0_de;
wire[7:0] wave0_r;
wire[7:0] wave0_g;
wire[7:0] wave0_b;
wire wave1_hs;
wire wave1_vs;
wire
2021-04-13 15:03:02
5.41MB