二维DCT算法 纯粹根据公式计算 实际计算结果有误差 可能原因是精度问题

不用matlab自带函数，自己编程实现二维DCT变换

二维DCT的Verilog实现，包含算法基础，模块设计等所需知识。The application note describes a 2 dimensional DCT function implemented on a Xilinx FPGA. Behavioral code is provided for the implementation on any Xilinx device. Some of the advantageous of the module includes parametrizeability and performance guarantee. The code can be further optimized by instantiating embedded adders and multipliers when targeting Virtex2 family. After an initial latency of 92 clock cycles, one DCT value is output at every clock.

基于二维DCT的自适应水印算法matlab实现参考源代码,根据图像块所包含的边缘信息的多少自适应嵌入不同的强度.

Zip file contains Verilog files (*.v) dct.v test_dct.v Vhdl file (*.vhd) dct.vhd The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i. The multiplier instantiation in the verilog files are used when targeting Virtex 2. For all other devices, the instantiations are commented out and the behavioral multiplier code is used. Test_dct contains the test bench which uses the input values as given in the reference "Image and Video Compression Standards" by V. Bhaskaran and K. Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v and idct.v files. The lower level vhdl files are dct.vhd and idct.vhd

是基于matlab的数字图像的二维傅立叶变换(FFT)以及二维离散余弦DCT变换，提供里详细代码，.m文件，还包括讲解