FPGA 读写rtc_ds1302实时时钟的Verilog逻辑源码Quartus工程文件+文档说明，RTC芯片型号ds1302，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。
module top(
//sys
input clk,
input rst_n,
output rtc_sclk,
output rtc_ce,
inout rtc_data,
output [5:0] seg_sel,
output [7:0] seg_data
);
wire[7:0] read_second;
wire[7:0] read_minute;
wire[7:0] read_hour;
wire[7:0] read_date;
wire[7:0] read_month;
wire[7:0] read_week;
wire[7:0] read_year;
seg_bcd seg_bcd_m0(
.clk (clk),
.rst_n (rst_n),
.seg_sel (seg_sel),
.seg_data (seg_data),
.seg_bcd ({read_hour,read_minute,read_second})
);
ds1302_test ds1302_test_m0(
.rst (~rst_n),
.clk (clk),
.ds1302_ce (rtc_ce),
.ds1302_sclk (rtc_sclk),
.ds1302_io (rtc_data),
.read_second (read_second),
.read_minute (read_minute),
.read_hour (read_hour),
.read_date (read_date),
.read_month (read_month),
.read_week (read_week),
.read_year (read_year)
);
endmodule
2021-04-12 20:03:51
4.50MB