XILINX XC6SLX16 Spartan6 FPGA开发板 Verilog设计50个逻辑DEMO源码，包括： 10_ip_ram 11_ip_fifo 12_uart_loopback_top 12_uart_top_rs232 13_rs485_uart_top 14_lcd_rgb_colorbar 15_lcd_rgb_char 16_top_hdmi_colorbar 17_hdmi_block_move_top 18_top_remote_rcv 19_top_cymometer 1_flow_led 20_e2prom_top 21_rtc_lcd 22_hs_ad_da 23_hs_dual_da 24_hs_dual_ad 25_audio_loopbck 26_top_ddr3_rw 27_audio_record 28_top_audio_sd 29_ov7725_lcd 2_key_led 30_ov7725_hdmi 31_ov5640_lcd 32_ov5640_hdmi 33_mt9v034_lcd 34_mt9v034_hdmi 35_top_sd_rw 36_sd_bmp_lcd 37_sd_bmp_hdmi 38_mdio_rw_test 39_eth_arp_test 3_key_beep 40_eth_udp_loop 41_eth_ddr3_lcd 42_eth_vedio_transmit 43_ov5640_hdmi_scale 44_ov7725_hdmi_rotate 45_ov5640_hdmi_yuv 46_ov5640_hdmi_median_filter 47_ov5640_hdmi_img_binarization 48_ov5640_hdmi_sobel 49_dual_ov5640_hdmi 4_touch_led 50_digital_recognition 5_breath_led 6_seg_led_static_top 7_seg_led_top 8_top_traffic 9_ip_pll XILINX XC6SLX16 Spartan6 超越者FPGA开发板原理图_V1.5.pdf