实验1 跑马灯实验
实验2 看门狗IWDG实验
实验3 按键输入
实验4 串口printf打印
实验5 串口Transmit打印
实验6 串口DMA收发
实验7 外部中断实验
实验8 RS485收发实验
实验9 时钟RTC DS1302实验
实验10 ADC实验
实验11 定时器timer2实验
实验12 SPI Flash读写实验
2024-08-29 11:10:56
468.57MB
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mt25q spi nor flash 单片机访问程序
2022-06-22 22:54:01
14KB
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BIOS 硬烧录软件以及驱动程序（其实就是libusb - sourceforge上能找到的），主要用于8个引脚的EEPROM芯片，如winbond 25x80VA等。USB端口烧录（非串口），windows下显示的设备是ejtag-tinyice。主板刷坏了就指望它了。
2022-02-15 09:57:44
701KB
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Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。
module spi_flash_top(
input sys_clk,
input rst,
output nCS,
output DCLK,
output MOSI,
input MISO,
input[15:0] clk_div,
input[3:0] cmd,
input cmd_valid,
output cmd_ack,
input[23:0] addr,
input[7:0] data_in,
input[8:0] size,
output data_req,
output reg[7:0] data_out,
output reg data_valid
);
localparam S_IDLE = 0;
localparam S_SE = 1;
localparam S_BE = 2;
localparam S_READ = 3;
localparam S_WRITE = 4;
localparam S_ACK = 5;
localparam S_CK_STATE = 6; //present state monitor
localparam S_WREN = 7;
wire spi_flash_cmd_ack;
reg[3:0] sub_cmd;
reg sub_cmd_valid;
reg[8:0] sub_size;
reg[4:0] state,next_state;
reg[7:0] state_reg;
wire sub_data_valid;
wire[7:0] sub_data_in;
wire[7:0] sub_data_out;
assign sub_data_in = data_in;
assign cmd_ack = (state == S_ACK);
always@(posedge sys_clk or posedge rst)
begin
if(rst==1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(cmd_valid && cmd == `CMD_BE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_SE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_READ)
next_state <= S_READ;
else if(cmd_valid && cmd == `CMD_PP)
next_state <= S_WREN;
else
next_state <= S_IDLE;
S_WREN:
if(spi_flash_cmd_ack && cmd == `CMD_BE)
next_state <= S_BE;
else if(spi_flash_cmd_ack && cmd == `CMD_SE)
next_state <= S_SE;
else if(spi_flash_cmd_ack && cmd == `CMD_PP)
next_state <= S_WRITE;
else
next_state <= S_WREN;
S_BE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;//读取状态寄存器
else
next_state <= S_BE;
S_SE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;
2021-12-12 09:08:55
4.81MB