适用于DOS系统下开发使用， PCI卡内存空间访问

集成PCI COM口驱动，选择CH35或CH38都可以，具体根据芯片组型号！

EP1C6Q240+BCM5421S+FP401千兆DVI显示控制PCI卡Pprotel99SE设计硬件原理图+PCB+FPGA逻辑源码,硬件4层板设计，大小为200x150mm，Protel 99se 设计的DDB后缀项目工程文件，包括完整无误的原理图和PCB印制板图，已经在项目中使用，可用Protel或 Altium Designer(AD)软件打开或修改，可作为你产品设计的参考。 核心器件如下: Library Component Count : 46 Name Description ---------------------------------------------------------------------------------------------------- 0006 24LC21LA/SN 4 HEADER HEADER 4 5208 8 HEADER HEADER 8 93C46 AT24C128 AT45DB041B-S U? BCM5421S GBIT-CHIP CAP Capacitor CAP+ CON6 Connector Cap Pol1 Polarized Capacitor (Radial) DIANGAN DIODE Diode DIP_XTAL DSO751S DVI_PLUG ELECTRO1 EP1C6Q240 FT245BM HEADER 2X2 HEADER 4X2 HEADER 9X2 HY57V653220 INDUCTOR2 Inductor Inductor LED LT1086MC MAGNETIC MYEPCS4 MYJTAG R RESISTOR RES RES1 RES2 RES4 SLDS119A SW-PB Switch TFP401 PCI64 USB_B ZENER2 alt_pll.v alt_ram_1024_24.v alt_ram_512_8.v clk_test.v deal_int.v dvi_test.v init_bcm5421.v init_set.v mii_man_cnt.v rec_pro_test.v report_face_t.v sdram_addr_test.v sdram_data_test.v sdram_init.v sdram_test_top.v test_vd0095.v tx_t_1.v usb_ctl.v usb_interface.v usb_phy_rx.v usb_phy_tx.v 配套的cyclone FPGA Verilog源码文件（非工程文件）如下：

EP1C6Q240+BCM5421S+FP401千兆DVI显示控制PCI卡PDF原理图PCB+AD集成封装库， ALTIUM工程转的PDF原理图PCB文件+AD集成封装库，已在项目中验证，可以做为你的设计参考。集成封装库器件列表： Library Component Count : 46 Name Description ---------------------------------------------------------------------------------------------------- 0006 24LC21LA/SN 4 HEADER HEADER 4 5208 8 HEADER HEADER 8 93C46 AT24C128 AT45DB041B-S U? BCM5421S GBIT-CHIP CAP Capacitor CAP+ CON6 Connector Cap Pol1 Polarized Capacitor (Radial) DIANGAN DIODE Diode DIP_XTAL DSO751S DVI_PLUG ELECTRO1 EP1C6Q240 FT245BM HEADER 2X2 HEADER 4X2 HEADER 9X2 HY57V653220 INDUCTOR2 Inductor Inductor LED LT1086MC MAGNETIC MYEPCS4 MYJTAG R RESISTOR RES RES1 RES2 RES4 SLDS119A SW-PB Switch TFP401 PCI64 USB_B ZENER2

PCI8系列 PCI9系列 PCI9054 linux驱动程序 PLX SDK Samples ================================================================ ABOUT This document provides a brief description of the samples included in the PLX SDK. Please refer to the source code in each sample & the PLX SDK User's Manual for additional details. The PLX samples are intended to demonstrate use of the PLX API. The samples are not intended for debug or real world applications, although they can be extended to complex applications. They should be treated as a reference for writing custom software that utilizes the PLX API. Not all samples work with all PLX devices. The PLX API supports numerous PLX chip families in PCI/PCIe, including 6000-series PCI-to-PCI bridges, 9000-series PCI-to-Local bus bridges, & 8000-series PCI/PCIe bridges & switches. Some samples are provided only for specific chip families. SAMPLES - ApiTest Simple application that calls various PLX APIs for a selected device & verifies return codes & parameters. The API calls made depend upon the type of device selected. - DSlave Demonstrates how to read/write from a PLX 9000 PCI BAR space using the PLX API/driver to perform the data transer. This operation is often referred to as "Direct Slave". - DSlave_BypassApi Similar to the 'DSlave' sample, except this sample uses the PLX API only to map a PCI BAR space directly to the application's virtual space. The application can then directly access the space via simple memory dereferencing, bypassing the PLX API/driver & resulting in greater performance, especially for small transfers. The application is responsible for initializing the BAR space, such as setup of translation/remap registers. - LocalToPciInt [9000-series & 8311] Demonstrates how to wait for a generic Local-to-PCI interrupt using the PLX Notification API. - NT_DmaTest [8000-series switches with DMA & NT support] Demonstrates using the DMA engine in a PLX 8000 switch to transfer data through a PLX